• 한국전자통신학회논문지
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• 제17권5호
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• pp.841-852
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• 2022

본 논문에서는 LCL 필터의 성능 검증을 위한 SPWM 제어기반의 3상 인버터 출력 파형 발생 장치를 개발하였다. 필터의 성능 검증을 위한 검사 신호를 얻기 위해 먼저, DSP 기반의 3상 SPWM 신호 생성 알고리즘을 개발하였으며, 동시에 3개의 하프 브리지 게이트 드라이버를 이용하여 SPWM 게이트 구동 신호들로부터 3상 SPWM 출력 파형을 발생시키기 위한 3상 전압형 인버터 회로를 설계하였다. 다음, 개발된 SPWM 기반 3상 인버터 출력 파형 장치의 검사 신호 발생 장치로서의 유효성을 검증하기 위해 하나의 LCL 필터가 실험, 제작되었으며, DSP 기반의 성능 검증 시스템이 실험적으로 구축되었다. 끝으로, 주어진 시비율을 가지는 출력 제어 실험에서 LCL 필터의 전 후의 3상 전압 파형을 비교함으로써 SPWM 기반 3상 인버터 출력파형 발생 장치의 유효성을 확인할 수 있었다.

• 한국전자통신학회논문지
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• 제12권6호
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• pp.1099-1106
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• 2017

본 논문에서는 신재생 에너지원인 태양광 발전을 위한 3상 인버터의 전력변환기술을 연구하였다. 태양광 인버터로는 정전압 공급 방식의 전압형 인버터, 제어기법으로는 SPWM 제어기법이 채택되었다. 태양광 인버터의 SPWM 제어기로는 강력한 고속 데이터 연산능력을 가지는 DSP가 채택되었으며, 배터리의 충전에 일정량의 전류를 공급하기 위해서 태양광 컨트롤러가 사용되었다. 끝으로, DSP를 주제어장치로 하는 소용량 3상 태양광 인버터 시스템이 시험, 제작되었으며, 실험을 통해서 SPWM 기반의 전력변환기능이 검증되었다.

• 대한전자공학회논문지
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• 제27권6호
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• pp.879-885
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• 1990

The geometrical algorithm for generating a 3-phase SPWM signal for VVVF (Variable Voltage, Variable Frequency) inverter drives is proposed. In this techniques, it is suitable for micro-processor based implementation since the pulsewiths are computable in real time from simple analytic expressions. System hardware consists of the inverter circuit and the 3-phase SPWM signal generating circuit. The inverter circuit is a 3-phase SPWM signal generating circuit is single board micro-processor consisting of Z-80A CPU, EPROMXI, CTC, PIO. The method of controlling VVVF at the inverter output is discussed here.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부A
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• pp.137-140
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• 1998

A new SPWM inverter using three-phase boost converter by auxiliary partial resonant with high power factor and high efficiency is proposed. The proposed boost converter is constructed by using a resonant network in parallel with the switch of the conventional boost converter. The devices are switched at zero voltage or zero current eliminating the switching loss. A new Partial resonant boost converter achieves zero-voltage switching (ZVS) or zero-current switching (ZCS) for all switch devices without increasing their voltage and current stresses. This paper introduces elimination of low-order harmonics compared with conventional SPWM inverter and SPWM inverter using three-phase boost converter by auxiliary Partial resonant.

• Journal of Power Electronics
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• 제16권2호
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• pp.490-497
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• 2016

The analysis of the switch status of each unit module of a cascaded multi-level inverter reveals that the working condition of the switch of a chopper arm causes unnecessary switching under the conventional unipolar sinusoidal pulse width modulation (SPWM). With an increase in the number of cascaded multilevel inverters, the superposition of unnecessary switching gradually occurs. In this work, we propose an improved SPWM strategy to reduce switching in cascaded multilevel inverters. Specifically, we analyze the switch state of the switch tube of a chopper arm of an H-bridge unit. The redundant switch is then removed, thereby reducing the switching frequency. Unlike the conventional unipolar SPWM technique, the improved SPWM method greatly reduces switching without altering the output quality of inverters. The conventional unipolar SPWM technique and the proposed method are applied to a five-level inverter. Simulation results show the superiority of the proposed strategy. Finally, a prototype is built in the laboratory. Experimental results verify the correctness of the proposed modulation strategy.

• 한국전자통신학회논문지
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• 제12권5호
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• pp.851-858
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• 2017

본 연구에서는 SPWM 구동방식의 단상 풀 브리지 인버터의 전압제어계를 설계하였다. 전압제어계는 단상 풀-브리지 인버터, 출력전압과 기준전압의 오차를 선형적으로 보상하기 위한 PI 제어기, 제어기 신호로부터 SPWM 방식을 이용하여 게이트 신호를 발생시키기 위한 PWM 구동회로, 인버터 출력 전압 파형을 정현 파형으로 필터링하기 위한 LC 필터로 구성하였다. 끝으로, EMTP-RV를 이용하여 PWM 구동방식을 기반으로 하는 단상 풀-브리지 인버터의 전압 제어계를 모델링하였고 수개의 기준전압에 대한 시뮬레이션 연구를 통해 출력전압이 정확하게 기준전압을 수렴하는 것을 확인함으로서 제어계 설계의 유효성을 확인할 수 있었다.

• Journal of Power Electronics
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• 제11권1호
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• pp.21-27
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• 2011

In this paper, an approach to reduce common-mode voltage (CMV) at the output of multilevel inverters using a phase opposition disposed (POD) sinusoidal pulse width modulation (SPWM) technique is proposed. The SPWM technique does not require computations therefore, this technique is easy to implement on-line in digital controllers. A good tradeoff between the quality of the output voltage and the magnitude of the CMV is achieved in this paper. This paper realizes the implementation of a POD-SPWM technique to reduce CMV using a five-level diode clamped inverter for a three phase induction motor. Experimental and simulation results demonstrate the feasibility of the proposed technique.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2003년도 춘계전력전자학술대회 논문집(2)
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• pp.511-515
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• 2003

This paper presents a novel prototype of the utility-interfaced sinusoidal pulse width modulated (SPWM) inverter using the high-frequency flyback transformer fur the small-scale solar photo-voltaic power conditioner (1kW - 4kW). The proposed SPWM power conditioner circuit with a high-frequency link has a function of electrical isolation, which is vital fur solar photovoltaic power conditioner systems with the viewpoint of safety and convenience. The discontinuous conduction mode (DCM) operation of the flyback transformer is also maintained to simplify the topology of the inverter circuit and control scheme. First, the operating principle of the proposed circuit is described far the understanding of the circuit parameters establishment. Then, the digitally constructed SPWM control scheme is presented. The proposed circuit is verified by the computer simulation and the prototype experiment.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제48권11호
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• pp.646-654
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• 1999

This paper deals with PWM patterns for harmonic reduction in inverter fed traction motors and the gear changing techniques for the variable speed drive of traction motor. GTOs are used as switching device of inverter because traction motor is a large load. To derive PWM rattern which can minimize the harmonics with the limited switching frequency, the output current and torque characteristic of SPWM and SHE PWM was analyzed. GTO inverter used for traction motor drive includes harmonics in the output current and torque by the limitation of switching frequency. However, the hybrid PWM method that adopt SPWM in the range of low frequency and SHE PWM in upper frequency range can achieve less harmonic characteristics in GTO inverters. If the traction motor is driven in variable speed by the proposed PWM pattern, 7 times of gear changing is needed. At the instant of the mode change, magnetic flux and torque may be altered and the large current flow. To reduce such an undesirable transient behavior, it is also presented the technique for the gear changing of inverter fed traction motor drive operated with the hybrid PWM. The results are verified by simulations and experiments.

• Journal of Power Electronics
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• 제19권6호
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• pp.1458-1466
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• 2019

Multilevel inverters have appeared as a successful and utilitarian solution in many power applications. The prime objective of an inverter is to keep the fundamental component of the output voltage of a multilevel inverter at a preferred value. Equally important is the need to keep the harmonic components in the output voltage within stated harmonic limits. Therefore, the basis of this research is to develop a harmonic minimization function that optimizes the switching angles of cascaded H-bridge multilevel inverter. Due to benefits of the Cuckoo Search (CS) algorithm, it is applied to determine the switching angles, which are further used to generate the switching pattern for firing the H-bridges of multilevel inverter. Simulation results are compared with SPWM based firing scheme. The switching frequency for SPWM firing scheme is taken as 200 Hz since the switching losses are increased when switching frequency is high. To validate the ability of Cuckoo Search optimized firing scheme in minimization of harmonics, experimental results obtained from hardware prototype of Five Level Cascaded H-Bridge Multilevel Inverter equipped with a FPGA controller are presented to verify the simulation results.