• Journal of the Korea Society of Computer and Information
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• v.3 no.2
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• pp.105-112
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• 1998

In this paper, we propose a ESP(Extended Scan Path) architecture for multi-board testing. The conventional architectures for board testing are single scan path and multi-scan path. In the single scan path architecture, the scan path for test data is just one chain. If the scan path is faulty due to short or open, the test data is not valid. In the multi-scan path architecture, there are additional signals in multi-board testing. So conventional architectures are not adopted to multi-board testing. In the case of the ESP architecture, even though scan path is either short or open, it doesn't affect remaining other scan paths. As a result of executing parallel BIST and IEEE 1149.1 boundary scan test by using the proposed ESP architecture, we observed that the test time is short compared with the single scan path architecture. By comparing the ESP architecture with single scan path responding to independency of scan path, test time and with multi-scan path responding to signal, synchronization, we showed that the architecture has improved results.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.10a
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• pp.1037-1040
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• 2002

In micro-stereolithography technology, fabrication conditions that include laser power, laser scan speed, laser scan pitch, and material property of photopolymer such as penetration depth and critical exposure are considered as major process variables. But the existing scan path generation methods based only on CAD model have not taken them into account, which has resulted in cross-section dimension of low accuracy. Thus, to enhance cross-section dimensional accuracy, the physical resin solidification n phenomena should be reflected in laser scan path generation and stage operating code. In this paper, multi-line experiments based on single line solidification model are performed. And the method for improving cross-section dimensional accuracy is presented, which is to apply the database based on experimental results to laser scan path generation.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.30 no.3 s.246
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• pp.334-341
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• 2006

A solid freeform fabrication (SFF) system using selective laser sintering (SLS) is currently recognized as a leading process and the SLS extends the applications to machinery and automobiles due to various employing materials. In order to fabricate a large part with SFF system, dual laser approach has been introduced. Since the building room is divided into two regions, each scan path for dual laser system is generated based on the single laser scan path. Scan paths for each laser have to be synchronized and consider mechanical strength against fracture at the interfaced region. This paper will address generation of single laser scan path which deals with special cases for unnecessary scan points and generation of dual laser scan path according to various divided regions to enhance mechanical strength. To evaluate the developed scan path method, the specimen will be fabricated and evaluated.

• The Transactions of the Korea Information Processing Society
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• v.3 no.7
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• pp.1924-1937
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• 1996

In this paper, we propose a ESP(Extended Scan Path) architecture for multi- board testing. The conventional architectures for board testing are single scan path and multi-scan path. In the single scan path architecture, the scan path for test data is just one chain. If the scan path is faulty due to short or open, the test data is not valid. In the multi-scan path architecture, there are additional signals in multi-board testing. So conventional architectures are not adopted to multi-board testing. In the case of the ESP architecture, even though scan paths either short or open, it doesn't affect remaining other scan paths. As a result of executing parallel BIST and IEEE 1149.1 boundary scan test by using, he proposed ESP architecture, we observed to the test time is short compared with the single scan path architecture. Because the ESP architecture uses the common bus, there are not additional signals in multi-board testing. By comparing the ESP architecture with conventional one using ISCAS '85 bench mark circuit, we showed that the architecture has improved results.

• Journal of Power Electronics
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• v.7 no.4
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• pp.278-285
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• 2007

Recently, plasma display panels (PDP) have become the most promising candidate in the market for large screen size flat panel displays. PDPs have many merits such as a fast display response time and wide viewing angle. However, there are still concerns about high cost because they require complex driving circuits composed of high power switching devices to generate various voltage waveforms for three operational modes of reset, scan, and sustain. Conventional PDP driving circuits use path switches for voltage separation and a scan switch to offer a scan voltage for reset and scan operations, respectively. In addition, there exist reset switches to initialize PDPs by regulating the wall charge conditions with ramp shaped pulses, which means the necessity of specific power devices for the reset operation. Because power for the plasma discharge accompanied by a large current is transferred to a panel via path switches, high power rating switches are used for path switches. Therefore, this paper proposes a novel low-cost PDP driving scheme achieved by not only eliminating path switches but also merging the function of reset switches into other switches used for sustain or scan operations. The simulated voltage waveforms of the proposed topology and experimental results implemented in a 42-inch panel to demonstrate the validity of using a new gate driver that merges the functions of power switches are presented.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1993.10a
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• pp.687-692
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• 1993

This paper deals with the generation of laser scan path for manufacturing 3-dimensional body using StereoLithography. The purpose of this study is to develop one module of the StersoLithography system(SLA) for Rapid Protyping and Manufacturing. AutoCAD system is used to supply CAD information from model. The X-Y controller which was made for a special purpose is used to test this system. The system software developed is composed of 3 main modules, the first module is calculating the boundary point os laser scan path. The scound module is generating final output file which is used to down load on the controller. The result of this study shows a good algorithm to generate laser scan path on the basis of simple mathematical background.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.72-84
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• 2001

The timings of all computational elements in the micropipeline circuits are important. The previous researches on path delay testing using scan methods make little account of the characteristic of the path delay tests that the second test pattern must be more controllable. In this paper, a new scan latch is proposed which is suitable to path delay testing of the micropipelines and has small area overhead. Results show that path delay faults in the micropipeline circuits using the new scan are testable robustly and the fault coverage is higher than the previous researches. In addition, the new scan latch for path delay faults testing in the micropipeline circuits can be easily expanded to the applications such as BIST for stuck-at faults.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.333-334
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• 2007

We propose a path planning method to decrease a inspection lead time of line scan camera in SMT(surface mount technology) in-line system. The inspection window area of printed circuit board should be minimized to consider the FOV(field of view) of line scan camera so that line scan inspector is going to find a optimal solution of path planning. We propose one of the hierarchical clustrering algorithm for a given board. Comparative simulation results are presented to verify the usefulness of proposed method.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.5
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• pp.749-758
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• 1995

There are many testable design techniques, among which Scan path and BIST techniques are mainly used. In this paper, the increase of design effectiveness is discussed, when these techniques are applied to the practical implementation of chips. The following techniques are presented : 1) Blocks are commonly used to reduce test time without hardware increase, 2) MUX is used to implement the shortest Scan path, 3) Scan register is used which controls and/or observes several blocks to avoid the increase of hardware.

• Journal of the Korean Society for Precision Engineering
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• v.13 no.12
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• pp.142-150
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• 1996

Nowadays, as the development paeiod of new products becomes even shorter, the importance of Rapid Prototyping Technology(RPT) has been rapidly increased. The major application of RPT is an early verification of product designs and quick production of prototypes for testing. Moreover, RPT is applied not only as a second tooling process such as mold making and investment casting but also as a creating some physical structure in medical field. Despite the remarkable progress of RPT, it is required to improve various problems resulting from application such as production time, accuracy and materials. This paper presents a laser scan path generation for accuracy of stereolithographicparts The methodology of laser scan path generation is discussed based on the stereolithography, The procedure of this research is as follows : 1) Input laser scanning conditions such as a laser beam diameter and a laser scanning interval, 2) Reconstruct original contours without self intersecting offset, 3) Calculate offset about reconstructed contours, 4) Calculate intersection points between horizontal or vertical lines and offset contours for internal hatch, 5) Decide laser shutter on/off points. The algorithm developed and programmed by C language is verified as an efficient method after testing a number of STL files of mechanical parts.