• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.1
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• pp.120-131
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• 2016

In this paper, a 512b MTP memory IP is designed by using MTP memory cells which are written by the FN (Fowler-Nordheim) tunneling method with only MV (medium voltage) devices of 5V which uses the back-gate bias, that is VNN (negative voltage). The used MTP cell consists of a CG (control gate) capacitor, a TG (tunnel gate) transistor, and a select transistor. To reduce the size of the MTP memory cell, just two PWs (P-wells) are used: one for the TG and the select transistors; and the other for the CG capacitor. In addition, just one DNW (deep N-well) is used for the entire 512b memory cell array. VPP and VNN generators supplying pumping voltages of ${\pm}8V$ which are insensitive to PVT variations since VPP and VNN level detectors are designed by a regulated voltage, V1V (=1V), provided by a BGR voltage generator.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.55-58
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• 2000

This paper describes a single transistor type ferroelectric field effect transistor (1T FeFET) memory celt scheme which can select one unit memory cell and program/read it. To solve the selection problem of 1T FeEET memory cell array, the row direction common well is electrically isolated from different adjacent row direction column. So, we can control voltage of common well line. By applying bias voltage to Gate and Well, respectively, we can implant IT FeEET memory cell scheme which no interface problem and can bit operation. The results of HSPICE simulations showed the successful operations of the proposed cell scheme.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.403-405
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• 2000

This paper describes a single transistor type ferroelectric field effect transistor (1Tr FeFET) memory cell scheme, which select one unit memory cell and program/read it. The well voltage can be controlled by isolating the common row well lines. Through applying bias voltage to Gate and Well, respectively, we implement If FeFET memory cell scheme in which interference problem is not generated and the selection of each memory cell is possible. The results of HSPICE simulations showed the successful operations of the proposed cell scheme.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.2
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• pp.113-117
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• 2007

We have investigated the effects of doping concentration in polysilicon floating gate on the endurance characteristics of the EEPROM cell haying the structure of spacer select transistor. Several samples were prepared with different implantation conditions of phosphorus for the floating gate. Results show the dependence of doping concentration in polysilicon floating gate on performance of EEPROM cell from the floating gate engineering point of view. All of the samples were endured up to half million programming/erasing cycle. However, the best $program-{\Delta}V_{T}$ characteristic was obtained in the cell doped at the dose of $1{\times}10^{15}/cm^{2}$.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.59-66
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• 2015

In this paper, we propose a method of improving the light-load efficiency of DC-DC buck converter using 4bit SAR-ADC (Successive Approximation ADC) for a LDO or a power transistor size selection technique. The proposed circuit selects power transistor sizes depending on load current so that improves the light-load efficiency of the DC-DC buck converter. For this, we select the power transistor size with a cross point of the switching loss and the conduction loss. Also, when the IC operates in standby mode or sleep mode, a LDO mode is selected for improving the efficiency. The proposed circuit selects power transistor sizes(X1, X2, X4, X8) with 4 bits and its efficiency is higher about the maximum of 25% at the light-load than that of a single transistor size. Input voltage and output voltage are 5V and 3.3V for maximum load currents of 500mA.

• ETRI Journal
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• v.37 no.6
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• pp.1188-1198
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• 2015

In this paper, a multi-time programmable (MTP) cell based on a $0.18{\mu}m$ bipolar-CMOS-DMOS backbone process that can be written into by using dual pumping voltages - VPP (boosted voltage) and VNN (negative voltage) - is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG_SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG_SENSE transistor; only two p-wells are used - one for the TG_SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n-well is used for the 256-bit MTP cell array. In addition, a three-stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of $1row{\times}64columns$ and a user memory area of $3rows{\times}64columns$, is newly proposed in this paper.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.205-210
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• 2001

In this paper, a novel compound mode logic based on the advantage of both CMOS logic and pass-transistor logic(PTL) is proposed. From the experimental results, the power-delay products of the compound mode logic is about 22% lower than that of the conventional CMOS logic, when we design a full adder. With the proposed logic, a high performance 32$\times$32-bit multiplier has been fabricated with 0.6um CMOS technology. It is composed of an improved sign select Booth encoder, an efficient data compressor based on the compound mode logic, and a 64-bit conditional sum adder with separated carry generation block. The Proposed 32$\times$32-bit multiplier is composed of 28,732 transistors with an active area of 1.59$\times$1.68 mm2 except for the testing circuits. From the measured results, the multiplication time of the 32$\times$32-bit multiplier is 9.8㎱ at a 3.3V power supply, and it consumes about 186㎽ at 100MHz.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.3
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• pp.39-46
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• 1994

CMOS LCD driving circuits using poly-Si TFT have been designed and basic blocks including test patterns have been fabricated. Column driver drives the pixels by block because polu-Si TFT can not operate at the speed of video signal. Row driver has mode selection circuit which can select a mode between interlacing mode and non-interlacing mode. Experimental results show shift register can operate at 1MHz colck frequency with 4pF load.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.51-51
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• 2001

본 논문에서는 CMOS 로직과 pass-transistor logic(PTL)의 장점만을 가진 새로운 복합모드로직(Compound Mode Logic)을 제안하였다. 제안된 로직은 VLSI설계에서 중요하게 부각되고 있는 저전력, 고속 동작이 가능하며 실제로 전가산기를 설계하여 측정 한 결과 복합모드 로직의 power-delay 곱은 일반적인 CMOS로직에 비해 약 22% 개선되었다 제안한 복합모드 로직을 이용하여 고성능 32×32-bit 곱셈기를 설계 제작하였다. 본 논문의 곱셈기는 개선된 사인선택(Sign Select) Booth 인코더, 4-2 및 9-2 압축기로 구성된 데이터 압축 블록, 그리고 carry 생성 블록을 분리한 64-bit 조건 합 가산기로 구성되어 있다. 0.6um 1-poly 3-metal CMOS 공정을 이용하여 제작된 32×32-bit 곱셈기는 28,732개의 트랜지스터와 1.59×l.68 ㎜2의 면적을 가졌다. 측정 결과 32×32-bit 곱셈기의 곱셈시간은 9.8㎱ 이었으며, 3.3V 전원 전압에서 186㎽의 전력 소모를 하였다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.509-518
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• 2023

In this paper, we designed a 4Kb poly-fuse OTP IP (Intellectual Property) required for analog circuit trimming and calibration. In order to reduce the BL resistance of the poly-fuse OTP cell, which consists of an NMOS select transistor and a poly-fuse link, the BL stacked metal 2 and metal 3. In order to reduce BL routing resistance, the 4Kb cells are divided into two sub-block cell arrays of 64 rows × 32 rows, with the BL drive circuit located between the two 2Kb sub-block cell arrays, which are split into top and bottom. On the other hand, in this paper, we propose a core circuit for an OTP cell that uses one poly-fuse link to one select transistor. In addition, in the early stages of OTP IP development, we proposed a data sensing circuit that considers the case where the resistance of the unprogrammed poly-fuse can be up to 5kΩ. It also reduces the current flowing through an unprogrammed poly-fuse link in read mode to 138㎂ or less. The poly-fuse OTP cell size designed with DB HiTek 90nm CMOS process is 11.43㎛ × 2.88㎛ (=32.9184㎛2), and the 4Kb poly-fuse OTP IP size is 432.442㎛ × 524.6㎛ (=0.227mm²).