• Journal of the Korean Society for Railway
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• v.9 no.6 s.37
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• pp.725-731
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• 2006

Hot Standby sparing system detecting faults by using software, and being tolerant any faults by using Hardware Redundancy is difficult to perform quantitative reliability prediction and to detect real time faults. Therefore, this paper designs Hot Standby sparing system using hardware basis self checking logic in order to overcome this problem. It also performs failure mode analysis of Hot Standby sparing system with designed self checking logic by using FMEA (Failure Mode Effect Analysis), and identifies reliability assessment of the controller designed by quantifying the numbers of failure development by using FTA (Fault Tree Analysis)

• Proceedings of the KSR Conference
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• 1999.05a
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• pp.299-306
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• 1999

The ${\mu}$-processor based-controlled system is widely used in railway signaling system. The railway signaling systems are highly required safety and reliability. It is necessary to have a fault-tolerant and fail safe concept in ${\mu}$-processor based railway signaling system. In this paper, several architectures and circuits of fault-tolerant computer system is reviewed. The basic concept of the fault-tolerant computer system will be adapted total self checking, strong fail safe, fault display circuit, logic testing circuit and system switching concepts.

• Proceedings of the Korean Information Science Society Conference
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• 2005.11b
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• pp.349-351
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• 2005

자가 적응 시스템을 무인 시스템(UWS: Unmanned Weapon Systems)에 적용하기 위한 다양한 연구가 이루어지고 있다. 자가 적응 시스템은 임무중인 시스템이 다양한 주변 환경 및 시스템의 변화에 따라 능동적으로 시스템 또는 임무수행을 위한 전략을 주정해 항상 최상의 성능을 발휘할 수 있도록 하는 능력을 갖춘 시스템을 말한다. 자가 적응 시스템에서 능동적으로 변화시킨 시스템의 아키텍처나 임무수행 전략이 유효한 것인지에 관한 검증을 수행한 후 시스템에 적용해야 한다. 기존의 대부분의 자가 적응 시스템에 대한 연구결과에서는 능동적으로 변화된 시스템이 임무수행에 적합한지에 대한 검증 방법을 제시해 주고 있지 않다. 본 연구에서는 UWS의 자가 적응 시스템이 임무수행 중 변화 되었을 때 미래의 발생할 사건에 대해 적절하게 적용 가능한지를 검증하기 위하여 시간적인 사건의 완전성을 검증하기에 적합한 Computation Tree Logic(CTL) 모델체킹(Model Checking)을 적용하여 자가 적응 시스템의 적응결과를 검증하는 방법을 제시하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.106-114
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• 2010

We proposed an unified design methodology and verification platform for giga-scale System on Chip (SoC). According to the growth of VLSI integration, the existing RTL design methodology has a limitation of a production gap because a design complexity increases. A verification methodology need an evolution to overcome a verification gap. The proposed platform includes a high level synthesis, and we develop a power-aware verification platform for low power design and verification automation using it's results. We developed a verification automation and power-aware verification methodology based on control and data flow graph (CDFG) and an abstract level language and RTL. The verification platform includes self-checking and the coverage driven verification methodology. Especially, the number of the random vector decreases minimum 5.75 times with the constrained random vector algorithm which is developed for the power-aware verification. This platform can verify a low power design with a general logic simulator using a power and power cell modeling method. This unified design and verification platform allow automatically to verify, design and synthesis the giga-scale design from the system level to RTL level in the whole design flow.