• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.222-222
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• 2000

The general dicing process cuts a semiconductor wafer to lengthwise and crosswise direction by using a rotating circular diamond blade. But inferior goods are made under the influence of several parameters in dicing such as blade, wafer, cutting water and cutting conditions. Moreover we can not applicable this dicing method to GaN wafer, because the GaN wafer is harder than the other wafer as GaAs. In older to overcome this problem, a new dicing process is necessary. This paper describes a new machine using scriber and precision servo mechanism in order to dice a semiconductor wafer.

• Journal of the Semiconductor & Display Technology
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• v.19 no.4
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• pp.18-21
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• 2020

Undetected wafer slip during the lift pin-down motion in semiconductor equipment may affect the center to edge variation, wafer warpage, and pattern misalignment in plasma equipment. Direct measuring of the amount of wafer slip inside the plasma process chamber is not feasible because of the hardware space limitation inside the plasma chamber. In this paper, we demonstrated a practice for the wafer lift pin-up and down motions with respect to the gear ratio, operating voltage, and pulse width modulation to maintain accurate wafer position using remote control linear servo motor with an experimentally designed chamber mockup. We noticed that the pin moving velocity and gear ratio are the most influencing parameters to be control, and the step-wised position control algorithm showed the most suitable for the reduction of wafer slip.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.55-60
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• 2020

The hard mask photo-resist strip inspection system for the semiconductor wafer manufacturing process inspects the position of the circuit pattern formed on the wafer by measuring the distance from the edge of the wafer to the strip processing area. After that, it is an inspection system that enables you to check the process status in real time. Process defects can be significantly reduced by applying a tester that has not been applied to the existing wafer strip process, edge etching process, and wafer ashing process. In addition, it is a technology for localizing semiconductor process inspection equipment that can analyze the outer diameter of the wafer and the state of pattern formation, which can secure process stability and improve wafer edge yield.

• Journal of the Semiconductor & Display Technology
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• v.21 no.1
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• pp.62-66
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• 2022

Semiconductor is one of the most internationally competitive areas among domestic industries, the major concern of which is the stability of the wafer manufacturing processes. The packaging process is the final step in wafer manufacturing. Problems in the wafer packaging process cause large losses. The vibrations are supposed to be the most important factors for the packaging quality. In this study, the structure of a packaging box was analyzed through experiments and computer simulations, and further the effects of design alterations to suppress the vibrations have been investigated. The final result shows that the vibrations can be reduced substantially to improve the stability of the structure.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2000.11a
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• pp.729-732
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• 2000

The general dicing process cuts a semiconductor wafer to lengthwise and crosswise direction by using a rotating circular diamond blade. But inferior goods are made under the influence of several parameters in dicing such as blade, wafer, cutting water and cutting condition. Moreover we can not applicable this dicing method to GaN wafer, because the GaN wafer is harder than the other wafer as GaAs. In order to overcome this problem, a new dicing process is necessary. This paper describes a new machine using scriber, breaker, and precision servo mechanism in order to dice an semiconductor wafer.

• Journal of Korean Institute of Industrial Engineers
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• v.29 no.2
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

• Journal of the Semiconductor & Display Technology
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• v.13 no.1
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• pp.13-17
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• 2014

Since the semiconductor manufacturing requires the silicon wafers with extraordinary degree of surface flatness, the surface polishing of wafers from ingot cutting is an important process for deciding surface quality of wafers. The present study introduces the development of wafer polishing equipment and, especially, the wafer polishing head that employs the forced self-driving of installed silicon wafer as well as the wax wafer mounting technique. A series of wafer polishing tests have been carried out to investigate the effects of self-driving function in wafer polishing head. The test results for wafer planarization showed that the LLS counts and SBIR of polished wafer surfaces were generally improved by adopting the self-driven polishing head in wafer polishing stations.

• Particle and aerosol research
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• v.5 no.1
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• pp.17-27
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• 2009

Particle deposition on a semiconductor wafer larger than 100 mm was studied experimentally and numerically. Particularly the electrostatic effect on particle deposition velocity was investigated. The experimental apparatus consisted of a particle generation system, a particle deposition chamber and a wafer surface scanner. Experimental data of particle deposition velocity were obtained for a semiconductor wafer of 200 mm diameter with the applied voltage of 5,000 V and PSL particles of the sizes between 83 and 495 nm. The experimental data of particle deposition velocity were compared with the present numerical results and the existing experimental data for a 100 mm wafer by Ye et al. (1991) and Opiolka et al. (1994). The present numerical method took into consideration the particle transport mechanisms of convection, Brownian diffusion, gravitational settling and electrostatic attraction in an Eulerian frame of reference. Based on the comparison of the present experimental and numerical results with the existing experimental results the present experimental method for a 200 mm semiconductor wafer was found to be able to present reasonable data.

• Journal of the Semiconductor & Display Technology
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• v.9 no.1
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• pp.23-28
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• 2010

In this paper, wafer drop from wafer guide mechanism, which is one of the serious problems in water transfer robot, is analyzed, and new wafer guide mechanisms are proposed to minimize this drop. Three types of new wafer guide mechanisms are proposed: roller type, gear type and L-shape rocker type. We choose one of the proposed mechanism, which is roller type, and verified this mechanism through real transfer experiment. Wafer picking up test is conducted with initial aligning error for simulating the wafer drop. Number of drop is compared between conventional mechanism and proposed mechanism. As a result, we can find the proposed mechanism can reduce the number of wafer drop dramatically.

• Journal of Institute of Control, Robotics and Systems
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• v.8 no.5
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• pp.419-424
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• 2002

After the patterning and probe process of wafer have been achieved, the dicing processing is necessary to separate chips from a wafer. The dicing process cuts a semiconductor wafer to lengthwise and crosswise directions to make many chips. The existing general dicing method is the mechanical cutting using a narrow circular rotating blade impregnated diamond particles or laser cutting. Inferior goods can be made by the mechanical or laser cutting unless several parameters such as blade, wafer, cutting water and cutting conditions are properly set. Moreover, we can not apply these general dicing method to that of GaN wafer, because the GaN wafer is harder than general semiconductor wafers such as GaAs, GaAsP, AIGaAs and so forth. In order to overcome these problems, this paper describes a new wafer dicing method using fixed diamond scriber and precision servo mechanism.