• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.4
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• pp.193-204
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• 2017

Various 3D-stacked DRAMs have been proposed to overcome the memory wall problem. Hybrid Memory Cube (HMC) is a true 3D-stacked DRAM with stacked DRAM layers on top of a logic layer. The logic die is mainly used to implement a memory controller for HMC, and it is connected through a high speed serial link called SerDes with a host that is either a processor or another HMC. In HMC, the serial link is crucial for both performance and power consumption. Therefore, it is important that the link is configured properly so that the required performance should be satisfied while the power consumption is minimized. In this paper, we propose a HMC system model included the high speed serial link to estimate performance accurately. Since the link modeling strictly follows the link flow control mechanism defined in the HMC spec, the actual HMC performance can be estimated accurately with respect to each link configuration. Various simulations are conducted in order to deduce the correlation between the HMC performance and the link configuration with regard to memory utilization. It is confirmed that there is a strong correlation between the achievable maximum performance of HMC and the link configuration in terms of both bandwidth and latency. Therefore, it is possible to find the best link configuration when the required HMC performance is known in advance, and finding the best configuration will lead to significant power saving while the performance requirement is satisfied.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.84-91
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• 2009

A high speed serial link transmitter using multi-level signaling is proposed. To achieve high data rate m high speed serial link, 4-pulse amplitude modulation (PAM) is used. By transmitting 2 bit data in each symbol time, high speed data transmission, two times than binary signaling, is achieved. The transmitter transmits current-mode output instead of voltage-mode output Current-mode output is much faster than voltage-mode output, so higher data transmission is available by increasing switching speed of driver. $2^5-1$ pseudo-random bit sequence (PRBS) generator is contained to perform built-in self test (BIST). The 4-PAM transmitter is designed in Dongbu HiTek $0.18{\mu}m$ CMOS technology and achieves 8 Gb/s, 160 mV of eye height with 1.8 V supply voltage. The transmitter consumes only 98 mW for 8 Gb/s transmission.

• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.697-699
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• 1999

2기가비트급 이상의 Serial-Link Chip에 적용되는 PLL의 특성은 lock-in-time이 빨라야하며 low VDD 동작을 확보해야 한다. 본 논문은 2.8기가비트급의 인터페이스 전송칩에 사용되는 PLL에 내부 전원 공급기를 설계하여 외부전원 3.3V시에 2.5V를 제공하며 이를 PFD/CP/VCO에 개별적 적용하는 제어방법 및 회로를 제안하며 이에 따르는 IPLL의 Lock-In-Time을 1mS 이내로 설계하였으며 외부동작 주파수는 100MHz이상이며 인터페이스 전송량은 2.8기가비트에 이른다. 저전압 설계를 통한 동작전류를 내부 전원 제어를 통해 순차적(Sequential Method)동작을 시킴으로 IPLL 동작시의 전류소모을 2mA이하로 제한하였다. 본 논문에서는 2.8기가비트급 인터페이스 전송칩에 적용한 IPLL의 회로 및 내부전원 공급기의 제어 방법 및 설계결과를 제안하며 이에 따르는 전송칩의 동작방법을 제안한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.79-85
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• 2009

The design of a 3.2 Gb/s serial link receiver in $0.18{\mu}m$ CMOS process is presented. The major factors limiting the performance of high-speed links are transmission channel bandwidth, timing uncertainty. The design uses a multi-level signaling(4-PAM) to overcome these problems. Moreover, to increase data bit-rate and lower BER, we designed this circuit by using a current mode amplifier, Current-mode Logic(CML) sampling latches. The 4-PAM receiver achieves 3.2 Gb/s and BER is less than $1.0\;{\times}\;10^{-12}$. The $0.5\;{\times}\;0.6\;mm^2$ chip consumes 49 mA at 3.2 Gb/s from a 1.8-V supply.

• Journal of Institute of Control, Robotics and Systems
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• v.13 no.4
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• pp.320-328
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• 2007

This paper presents a stiffness modeling of a low-DOF parallel robot, which takes into account of elastic deformations of joints and links, A low-DOF parallel robot is defined as a spatial parallel robot which has less than six degrees of freedom. Differently from serial chains in a full 6-DOF parallel robot, some of those in a low-DOF parallel robot may be subject to constraint forces as well as actuation forces. The reaction forces due to actuations and constraints in each serial chain can be determined by making use of the theory of reciprocal screws. It is shown that the stiffness of an F-DOF parallel robot can be modeled such that the moving platform is supported by 6 springs related to the reciprocal screws of actuations (F) and constraints (6-F). A general $6{\times}6$ stiffness matrix is derived, which is the sum of the stiffness matrices of actuations and constraints, The compliance of each spring can be precisely determined by modeling the compliance of joints and links in a serial chain as follows; a link is modeled as an Euler beam and the compliance matrix of rotational or prismatic joint is modeled as a $6{\times}6$ diagonal matrix, where one diagonal element about the rotation axis or along the sliding direction is infinite. By summing joint and link compliance matrices with respect to a reference frame and applying unit reciprocal screw to the resulting compliance matrix of a serial chain, the compliance of a spring is determined by the resulting infinitesimal displacement. In order to illustrate this methodology, the stiffness of a Tricept parallel robot has been analyzed. Finally, a numerical example of the optimal design to maximize stiffness in a specified box-shape workspace is presented.

• Journal of Institute of Control, Robotics and Systems
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• v.18 no.8
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• pp.731-737
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• 2012

In this paper the usage of Bluetooth in networked control systems is described. ACL links and commonly used serial port profile built on top of ACL links are analyzed and their problems such as unpredictable latency are discovered. SCO link packet scheduling, latency estimation and setup procedure are examined. SCO link is suggested as proper link for NCS, due to its low latency and low variance. Smith predictor use for latency compensation is described and its impact on control performance is estimated. A number of experiments on DC motor position control are performed and control performance of system utilizing SCO link with and without Smith predictor is proved to be higher than control performance of system utilizing ACL link.

• International Journal of Naval Architecture and Ocean Engineering
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• v.13 no.1
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• pp.848-857
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• 2021

This paper proposes an efficient approach based on a machine learning technique to predict the local stresses on mooring chain links. Three-link and multi-link finite element analyses were conducted for a target chain link of D107 with steel grade R4; 24,000 and 8000 analyses were performed, respectively. Two serial Artificial Neural Network (ANN) models based on a deep multi-layer perceptron technique were developed. The first ANN model corresponds to multi-link analyses, where the input neurons were the tension force and angle and the output neurons were the interlink angles. The second ANN model corresponds to the three-link analyses with the input neurons of the tension force, interlink angle, and the local stress positions, and the output neurons of the local stress. The predicted local stresses for the untrained cases were reliable compared to the numerical simulation results.

• ETRI Journal
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• v.32 no.5
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• pp.713-721
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• 2010

E-textile technology has earned a great deal of interest in many fields; however, existing wearable network protocols are not optimized for use with conductive yarn. In this paper, some of the basic properties of conductive textiles and requirements on wearable personal area networks (PANs) are reviewed. Then, we present a wearable personal network (WPN), which is a four-layered wearable PAN using bus topology. We have designed the WPN to be a lightweight protocol to work with a variety of microcontrollers. The profile layer is provided to make the application development process easy. The data link layer exchanges frames in a master-slave manner in either the reliable or best-effort mode. The lower part of the data link layer and the physical layer of WPN are made of a fabric serial-bus interface which is capable of measuring bus signal properties and adapting to medium variation. After a formal verification of operation and performances of WPN, we implemented WPN communication modules (WCMs) on small flexible printed circuit boards. In order to demonstrate the behavior of our WPN on a textile, we designed a WPN tutorial shirt prototype using implemented WCMs and conductive yarn.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1193-1196
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• 2003

This paper proposes a 2x oversampling method with a smart sampling for a clock and data recovery(CDR) circuit in a 2.5Gbps serial data link. In the conventional 2x oversampling method, the "bang-bang" operation of the phase detection produces a systematic jitter in CDR. The smart sampling in phase detection helps the CDR to remove the "bang-bang" operation and to improve the jitter performance. The CDR with the proposed 2x oversampling method is designed using Samsung 0.25${\mu}{\textrm}{m}$ process parameters and verified by simulation. Simulation result shows the proposed 2x oversampling method removes the systematic jitter.e systematic jitter.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1185-1188
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• 2003

This paper describes a design for a 2.5Gb/s serial data link CMOS transceiver based on the InfiniBand$^{TM}$ specification. The transceiver chip integrates data serializer, line driver, Tx PLL, deserializer, clock recovery, and lock detector. The designed transceiver is fabricated in a 0.25 ${\mu}{\textrm}{m}$ CMOS mixed-signal, 1-poly, 5-metal process. The first version chip occupies a 3.0mm x 3.3mm area and consumes 450mW with 2.5V supply. In 2.5 Gbps, the output jitter of transmitter measured at the point over a 1.2m, 50Ω coaxial cable is 8.811ps(rms), 68ps(p-p). In the receiver, VCO jitter is 18.5ps(rms), 130ps(p-p), the recovered data are found equivalent to the transmitted data as expected. In the design for second version chip, the proposed clock and data recovery circuit using linear phase detector can reduce jitter in the VCO of PLL.L.