• Journal of KIISE
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• v.41 no.11
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• pp.885-891
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• 2014

A hash function is an essential cryptographic algorithm primitive that is used to provide integrity to many applications such as message authentication codes and digital signatures. In this paper, we introduce a concept and test method for a Cryptographic Algorithm Validation Program (CAVP). Also, we design an SHA-3 CAVP program and implement an SHA-3 algorithm in 16bit-UICC. Finally, we compare the efficiency of SHA-3 with SHA-2 and evaluate the exellence of the SHA-3 algorithm.

• Review of KIISC
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• v.19 no.4
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• pp.44-52
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• 2009

2005년 중국의 Wang 교수 연구팀에 의해 SHA-1에 대한 충돌쌍 공격이 발표됨에 따라, SHA-1 대신 SHA-2를 사용하도록 하였다. 아직까지 SHA-2에는 SHA-1과 같은 문제점이 발생하지 않고 있지만, SHA-1과 설계 논리가 유사한 SHA-2에 문제점이 생겼을 경우 대체 알고리즘이 부재한 현 상황에 따라 SHA-3 알고리즘 개발의 필요성이 제기되었다. 이에 미국 국립기술 표준원 (NIST, National Institute of Standards and Technologies)는 신규 표준 해쉬 알고리즘을 개발을 위하여 2007년부터 2012년까지 6년간의 "SHA-3 프로젝트"를 시작하였다. 2008년 11월 1일 64개의 알고리즘이 제출되었으며, 12월 11일 51개의 알고리즘이 1 후보 알고리즘으로 선정되었다. 2009년 7월 현재, 10개의 알고리즘이 제안자에 의해 철회되어 41개의 알고리즘이 1 라운드에서 심사되고 있다. 본 논문에서는 SHA-3 개발의 요구 사항과 현재까지 SHA-3 개발 동얄을 서술한다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.25 no.4
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• pp.749-757
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• 2015

As the smart era, the use of smart devices is increasing. Smart devices are widely used to provide a human convenience, but there is a risk that information is exposed. The smart devices to prevent this problem includes the encryption algorithm. Among them, The hash function is an encryption algorithm that is used essentially to carry out the algorithm, such as data integrity, authentication, signature. As the issue raised in the collision resistance of SHA-1 has recently been causing a safety problem, and SHA-1 hash function based on the current standard of SHA-2 would also be a problem in the near future safety. Accordingly, NIST selected KECCAK algorithm as SHA-3, it has become necessary to implement this in various environments for this algorithm. In this paper, implementation of KECCAK algorithm. And SHA-2 On The ARM-11 processor, and compare performance.

• The KIPS Transactions:PartC
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• v.19C no.3
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• pp.179-184
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• 2012

Due to the absence of an alternative algorithm SHA-2, NIST (National Institute of Standards and Technology) is proceeding to development project of SHA-3. NIST announced five candidates of the final round at the end of 2010. Side-channel attack scenarios of five candidates for SHA-3 final round have been proposed. In this paper, we prove the possibility of the analysis against 32-bit modular addition by 8-bit blocks from our experiment on ARM chip board with a register size of 32-bit. In total we required 9700 power traces to successfully recover the 128-bit secret key for the attack against.

• Journal of Acupuncture Research
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• v.22 no.3
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• pp.53-67
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• 2005

Objective : The purpose of this study is to observe the effects of Scolopendrid Aqua-acupuncture applied to the L14 on galactosamine-induced liver injury in rats. Methods : In this study, the experimental rats were divided four groups(Control group, SHA-1, SHA-2, SHA-3 group). In the Control group, we first injected galactosamine and then didn`t treated. In the SHA-1, SHA-2, SHA~3 group, we first Injected galactosamine and then injected Scolopendrid aqua-acupuncture applied to L14, each 0.083mg/kg, 0.017 mg/kg, 0.008mg/kg. We observed the changes of GOT, GPT, ${\gamma}$-GTP, Total bilirubin, LDH, ALP, Total cholesterol, Triglyceride, HDL-cholesterol, WBC, RBC, HGB, Hct. Results & Conclusion: 1. In the change of GPT content, as compared with control group, SHA-2, SHA-3 groups were significantly decreased. 2. In the change of ${\gamma}$-GTP content, as compared with control group, SHA-1, SHA-2 groups were significantly decreased. 3. In the change of Total bilirubin content, as compared with control group, SHA-2 group was significantly decreased.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.1
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• pp.115-125
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• 2011

Cryptographic hash functions are also called one-way functions and they ensure the integrity of communication data and command by detecting or blocking forgery. Also hash functions can be used with other security protocols for signature, authentication, and key distribution. The SHA-1 was widely used until it was found to be cryptographically broken by Wang, et. al, 2005. For this reason, NIST launched the SHA-3 competition in November 2007 to develop new secure hash function by 2012. Many SHA-3 hash functions were proposed and currently in review process. To choose new SHA-3 hash function among the proposed hash functions, there have been many efforts to analyze the cryptographic secureness, hardware/software characteristics on each proposed one. However there are few research efforts on the SHA-3 from the point of power consumption, which is a crucial metric on hardware module. In this paper, we analyze the power consumption characteristics of the SHA-3 hash functions when they are made in the form of ASIC hardware module. Also we propose power efficient hardware architecture on Luffa, which is strong candidate as a new SHA-3 hash function. Our proposed low power architecture for Luffa achieves 10% less power consumption than previous Luffa hardware architecture.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.187-189
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• 2018

In this paper, the optimal design conditions for hardware implementation of the Secure Hash Algorithm3-512 (SHA3-512) hash function were analyzed. Five SHA3-512 hash cores with data-path of 64-bit, 320-bit, 640-bit, 960-bit, and 1600-bit were designed, and their functionality were verified by RTL simulation. Based on the results synthesized with Xilinx Virtex-5 FPGA device, we evaluated the performance of the SHA3-512 hash cores, including maximum frequency, throughput, and occupied slices. The analysis results show that the best hardware performance of SHA3-512 hash core can be achieved by designing it with 1600-bit data-path.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.6
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• pp.1075-1082
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• 2017

This paper describes a design of hash processor which can execute new hash algorithm, SHA-3 and extendable-output function (XOF), SHAKE-256. The processor that consists of padder block, round-core block and output block maximizes its performance by using the block-level pipelining scheme. The padder block formats the variable-length input data into multiple blocks and then round block generates SHA-3 message digest or SHAKE256 result for multiple blocks using on-the-fly round constant generator. The output block finally transfers the result to host processor. The hash processor that is implemented with Xilinx Virtex-5 FPGA can operate up to 220-MHz clock frequency. The estimated maximum throughput is 5.28 Gbps(giga bits per second) for SHA3-512. Because the processor supports both SHA-3 hash algorithm and SHAKE256 algorithm, it can be applicable to cryptographic areas such as data integrity, key generation and random number generation.

• Journal of IKEEE
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• v.22 no.4
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• pp.886-895
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• 2018

This paper describes a hardware design of the Secure Hash Algorithm-3 (SHA-3) hash functions that are the latest version of the SHA family of standards released by NIST, and an implementation of ARM Cortex-M0 interface for security SoC applications. To achieve an optimized design, the tradeoff between hardware complexity and performance was analyzed for five hardware architectures, and the datapath of round block was determined to be 1600-bit on the basis of the analysis results. In addition, the padder with a 64-bit interface to round block was implemented in hardware. A SoC prototype that integrates the SHA-3 hash processor, Cortex-M0 and AHB interface was implemented in Cyclone-V FPGA device, and the hardware/software co-verification was carried out. The SHA-3 hash processor uses 1,672 slices of Virtex-5 FPGA and has an estimated maximum clock frequency of 289 Mhz, achieving a throughput of 5.04 Gbps.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.6 no.9
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• pp.2388-2404
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• 2012

Cryptographic hash functions are widely used in many information security applications like digital signatures, message authentication codes (MACs), and other forms of authentication. In response to recent advances in cryptanalysis of commonly used hash algorithms, National Institute of Standards and Technology (NIST) announced a publicly open competition for selection of new standard Secure Hash Algorithm called SHA-3. One important aspect of this competition is evaluation of hardware performances of the candidates. In this work we present efficient hardware implementations of SHA-3 finalists: JH, Keccak and Skein. We propose high speed architectures using Look-Up Table (LUT) resources on FPGAs, to minimize chip area and to reduce critical path lengths. This approach allows us to design data paths of SHA-3 finalists with minimum resources and higher clock frequencies. We implemented and investigated the performance of these candidates on modern and latest FPGA devices from Xilinx. This work serves as performance investigation of leading SHA-3 finalists on most up-to-date FPGAs.