• International Journal of Precision Engineering and Manufacturing
• /
• v.5 no.2
• /
• pp.39-45
• /
• 2004

Atomic Force Microscope (AFM) has been widely used in micro/nano-scale studies and applications for the last few decades. In this work, wear characteristics of silicon-based AFM tip was investigated. AFM tip shape was observed using a high resolution SEM and the wear coefficient was approximately calculated based on Archard's wear equation. It was shown that the wear coefficient of Si and ${Si}_3$$N_4$ tips were in the range of ${10}^{-1}$~${10}^{-3}$and ${10}^{-3}$~${10}^{-4}$, respectively. Also, the effect of relative humidity and sliding distance on adhesion-induced tip wear was investigated. It was found that the tip wear has more severe for harder counter surface materials. Finally, the probable wear mechanism was analyzed from the adhesive and abrasive interaction point of view.

• Journal of the Korean Electrochemical Society
• /
• v.9 no.2
• /
• pp.84-88
• /
• 2006

The effects of tip voltage, deflection setpoint, and tip velocity on height of $SiO_2$ line drawn by local anodization on Si wafer using scanning probe microscope were investigated. No local anodization was detected at smaller than -3 V of tip voltage. The line height increased at rate of 0.47 nm/V when the tip voltage is stronger than -3 V at $1{\mu}m/s$ tip velocity. From deflection setpoint, mechanical force between tip and substrate could be calculated and the threshold farce was $12\sim18nN$. The height of anodized $SiO_2$ lines is independent of the magnitude of force above the threshold force. The line height decreased as increasing the tip velocity and limited to 0.7 nm at -5 V tip voltage.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.48 no.9
• /
• pp.662-664
• /
• 1999

We fabricated AC-TFEL device having cone-shaped Si micro-tip reflector array based on the process which have been conventionally employed for the Si-tip field emitter array in FED system. As a result, the AC-TFEL device having a new geometrical structure could generate well concentrated visible white-light from 3600 reflectors/pixel under bipolar pulse excitation mode only by edge-emission mechanism.

• Journal of the Microelectronics and Packaging Society
• /
• v.7 no.3
• /
• pp.27-29
• /
• 2000

For the DLC-coaled Si-tip FEA, the modified lift off-process, by which DLC coated on both gate electrode surface and gate insulator in the gate aperture could be removed, was proposed. In the process, the Al sacrificial layer was deposited on a tilted and rotated substrate by an e-beam evaporation, and DLC film was coated on the substrate by PA-CVD method. Afterward the DLC was perfectly removed except the DLC films coated on emitter tips by etch-out of Al sacrificial layer. Current-voltage curves and current fluctuation of the DLC-coated Si-tip FEA showed that the proposed lift-off process played an important role in decreasing gate leakage current and stabilizing omission current.

• Korean Journal of Materials Research
• /
• v.10 no.2
• /
• pp.124-127
• /
• 2000

A new triode type Ti-silicided Si FEA(field emitter array) was realized by Ti-silicidation of Ti coated Si FEA and its field emission properties were investigated. In the fabricated device, the field emission properties through the unit pixel with $200{\mu\textrm{m}}{\times}200{$\mu\textrm{m}}$ tip array in the area of $1000{\mu\textrm{m}}{\times}1000{$\mu\textrm{m}}$ were as follows : the turn-on voltage was about 70V under high vacuum condition of $10^8Torr$, and the field emission current and steady state current degradation were about 2nA/tip and 0.3%/min under the bias of $V_A=500V\;and\;V_G=150V$. The low turn-on voltage and the high current stability during long term operation of the Ti silicided Si FEA were due to the thermal and chemical stability and the low work function of silicide layer formed at the surface of Si tip.

• Journal of the Korean institute of surface engineering
• /
• v.47 no.6
• /
• pp.362-367
• /
• 2014

We report the design, fabrication of a $Si_3N_4$ probe and calculation of its mechanical properties for DPN(dip pen nanolithography), which consists of dual tips. Concept of dual tip probe is to employ individual tips on probe as either an AFM tip for imaging or a writing tip for nano patterning. For this, the dual tip probe is fabricated using low residual stress $Si_3N_4$ material with LPCVD deposition and MEMS fabrication process. On the basis of FEM analysis we show that the functionality of dual tip probe for imaging is dependent on the dimensions of dual tip probe, and high ratio of widths of beam areas is preferred to minimize curvature variation on probe.

• Korean Journal of Materials Research
• /
• v.10 no.4
• /
• pp.301-304
• /
• 2000

A new triode type Co-silicided Si FEA(field emitter array) was realized by Co-silicidation of Co coated Si FEA and its field emission properties were investigated. The field emission properties of the fabricated device through the unit pixel with $45{\times}45$ tip array in the area of $250{\mu\textrm{m}}{\times}250{\mu\textrm{m}}$ under high vacuum condition of $10^{-8}Torr$ were as follows : the turn-on voltage was about 35V and the anode current was about $1.2\mu\textrm{A}(0.6㎁/tip)$ at the bias of $V_A=500V\;and\; V_G=55V$. The fabricated device showed the stable electrical characteristics without degradation of field emission current for the long term operation except for the initial transient state. The low turn-on voltage and the high current stability of the Co-silicided Si FEA were due to the thermal and chemical stability and the low work function of silicide layer formed at the surface of Si tip.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.48 no.7
• /
• pp.521-524
• /
• 1999

Nb silicide was formed on the Si micro-tip arrays in order to improve field emission properties of Si-tip field emitter array. After silicidization of the tips, the etch-back process, by which gate insulator, gate electrode and photoresist were deposited sequentially and gate holes were defined by removing gradually the photoresist by $O_2$ plasma from the surface, was applied. Si nitride film was used as a protective layer in order to prevent oxygen from diffusion into Nb silicide layer and it was identified that the NbSi2 was formed through annealing in $N_2$ ambient at $1100^{\circ}C$ for 1 hour. By the Nb silicide coating on Si tips, the turn-on voltage was decreased from 52.1 V to 32.3 V and average current fluctuation for 1 hour was also reduced from 5% to 2%. Also, the fabricated Nb silicide-coated Si tip FEA emitted electrons toward the phosphor and light emission was obtained at the gate voltage of 40~50 V.

• Proceedings of the KIEE Conference
• /
• 1995.07c
• /
• pp.1428-1430
• /
• 1995

In this study we fabricate Knife type Si-tip array using (110) Si wafer. We can fabricate vertical structure by anisotropic etching using EPW and observe it by SEM. After the step, we perform isotropic etching and oxidation sharpening of the structure and also observe it by SEM, respectively. The purpose of isotropic etching is to reduce the oxidation time. We attain a optimal tip whose radius is about $100{\AA}$ after anisotropic etching 2.25 min.+isotropic etching 5 min.+oxidation 1 hour and 23 min.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2010.06a
• /
• pp.351-351
• /
• 2010

Nanoscale patterning using an atomic force microscope tip induced scratching was systematically investigated in AI thin film on 4H-SiC. To identify the effects of the scratch parameters, including the tip loading force, scratch speed, and number of scratches, we varied each parameters and evaluated the major parameter which has intimate relationship with the scale of patterns. In this work, we present the successful demonstration of nano patterning of Al thin film on a 4H-SiC substrate using an AFM scratching and evaluated the scratch parameters on Al/4H-SiC.