• Transactions on Electrical and Electronic Materials
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• v.18 no.2
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• pp.62-65
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• 2017

In this paper, three DC Block designs are presented which efficiently meet the need of modern-day compactsize wireless communication systems. As one of the important parts of a complete system design, the proposed microstrip-based DC block with coupled transmission lines efficiently attenuates unwanted frequencies that cause damage to the system. The compact-sized DC block structures are created by incorporating an extended coupled-line section with a radial stub, an enveloped coupled-line section, and using alternate up-down meandering techniques. The structures are analyzed for the L-Band using a high-resistive silicon substrate. At a resonating frequency of 1.575 GHz, the designed DC Block structures have a return loss better than -10 dB, an insertion loss of around -1 dB, and also possess wide pass-band characteristics.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.10 no.6
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• pp.146-151
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• 2011

Wax spin coating is a part of several wafer handling processes in the silicon wafer polishing station. It is important to ensure the wax layer free of contamination to achieve the high degree of planarization on wafers after wafer polishing. Three-dimensional air flow characteristics in a wax spin coater are numerically investigated using computational fluid dynamics techniques. When the bottom of the wax spin coater is closed, there exists a significant recirculation zone over the rotating ceramic block. This recirculation zone can be the source of wax layer contamination at any rotational speed and should be avoided to maintain high wafer polishing quality. Thus, four air suction ducts are installed at the bottom of the wax spin coater in order to control the air flow pattern over the ceramic block. Present computational results show that the air suction from the bottom is quite an effective method to remove or minimize the recirculation zone over the ceramic block and the wax coating layer.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.181-186
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• 2005

We fabricated thin films of polystyrene-block-poly(methyl methacrylate)(PS -b-PMMA) on the self-assembled monolayers(SAM) of 3-(p-methoxyphenyl)propyltrichlorosilane(MPTS) on silicon wafers. Cylindrical nanodomains of PMMA or PS were oriented perpendicular to the surface of silicon wafers due to the neutral affinity of the SAM to PS and PMMA blocks. By selective removal of the PMMA block with UV irradiation and washing, nanoporous films and nanorod assemblies were produced. The nanoporous film can be used for a nanolithographical mask.

• Journal of Korean Institute of Industrial Engineers
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• v.29 no.2
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

• The Journal of the Society of Korean Medicine Diagnostics
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• v.17 no.3
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• pp.225-232
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• 2013

Objectives The aim of this study is to design a part in contact with the face of computerized tongue diagnosis system (CTDS), so that external light is effectively shielded even if the facial appearance and degree of protrusion differ when a patient opens or closes his/her jaws. Methods Each of the 4 researchers manually produced clay models of the part in contact with the face of CTDS. Shielding and contact feeling of the clay models were evaluated by 20 assessors. Based on the evaluation, we selected the appropriate model and produced the final silicon model. Then we evaluated the performance of the shielding of the completed silicon model. We took tongue pictures of 60 participants with a CTDS applying the silicon model in condition with external light and without it. The color values in RGB color model and gray scale of the tongue pictures in condition with external light were compared with those without external light. Results There was no significant difference between the color values of the picture taken in condition with external light and those without external light. Conclusions We concluded that the produced part in contact with the face of CTDS can effectively block out the external light.

• Journal of information and communication convergence engineering
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• v.12 no.1
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• pp.46-52
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• 2014

This article presents key research needs in three-dimensional integrated circuit (3D IC) architectural floorplanning. Architectural floorplaning is done at a very early stage of 3D IC design process, where the goal is to quickly evaluate architectural designs described in register-transfer level (RTL) in terms of power, performance, and reliability. This evaluation is then fed back to architects for further improvement and/or modifications needed to meet the target constraints. We discuss the details of the following research needs in this article: block-level modeling, through-silicon-via (TSV) insertion and management, and chip/package co-evaluation. The goal of block-level modeling is to obtain physical, power, performance, and reliability information of architectural blocks. We then assemble the blocks into multiple tiers while connecting them using TSVs that are placed in between hard IPs and inside soft IPs. Once a full-stack 3D floorplanning is obtained, we evaluate it so that the feedback is provided back to architects.

• Journal of the Korean institute of surface engineering
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• v.37 no.1
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• pp.22-27
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• 2004

Copper electroforming process has been applied to duplicate Koryo Tripitaka (Taejang'kyong), wooden printing block. Thin copper replica printing plates of 1 mm thickness was successfully manufactured from the printing face (54.5${\times}$25.5 cm) of wooden printing plate. Major processes are (1) silicon rubber replication of the master (2) silvering on silicon rubber (3) copper electroforming (4) separation of copper from the silicon mandrel (5) final coloring by brass plating and trimming. This process has various Potential applications in making thin metallic objects such as plaques, statues, bust and hollow metal objects for jewelry.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.249-250
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• 2008

In this paper, we propose the single polycrystalline silicon flash EEPROM IC with a new structure which does not need the high voltage switching circuit. The design of high voltage switching circuits which are needed for the data program and erase, has been an obstacle to develop the single-poly EEPROM. Therefore, we has proposed the new cell structure which uses the low voltage switching circuits and has designed the full chip. A new single-poly EEPROM cell is designed and the full chip including the control block, the analog block, row decoder block, and the datapath block is designed. And the each block is verified by using the computer simulation. In addition, the full chip layout is performed.

• Journal of Advanced Marine Engineering and Technology
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• v.22 no.6
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• pp.800-808
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• 1998

In this study the thermal stress distribution and deformantion characteristics resulting from the nonuniform temperature fields of the cylinder block of a light 3-cylinder 4-stroke gasoline engine were analyzed using the 3-dimensional finite element method. The temperature distributions req-uisite for the thermoelastic behavior alalysis were obtained from the steady-state heat conduction analysis performed on the basis of experimental data. in order to examine the effect of a ceramic material the cylinder liner was replaced by the silicon nitride($Si_{3}N_{4}$) and its thermal behaviors were compared with those of the original block.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.5
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• pp.263-266
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• 2006

An optical microphone was developed using a dual-core multi-mode fiber block and a membrane type micromirror. The fiber block serves as a compact optical head, and the micromirror as a reflective diaphragm. The micromirror is designed to be suspended through a silicon bar connected t a frame, allowing for displacement induced by acoustic waves. The optical head is implemented by integrating two multi-mode fibers in a single block, and used to transfer light signals between it and the diaphragm. For the assembled microphone, its static characteristics were observed to reveal the operating point defined as the optimum distance between the optical head and the diaphragm. And its dynamic response was tested to exhibit a frequency bandwidth of 3 kHz with the variation of $\sim5dB$.