• Title/Summary/Keyword: Silicon wafer

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A Study on Low Temperature Bonding of Si-wafer by Surface Activated Method (표면활성화법에 의한 실리콘웨이퍼의 저온접합에 관한연구)

    • Journal of the Korean Society of Manufacturing Technology Engineers
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    • v.6 no.4
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    • pp.34-38
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    • 1997
  • This paper presents a joining method by using the silicon wafer in order to apply to joint to the 3-dimensional structures of semiconductor device, high-speed , high integration, micro machine, silicon integrated sensor, and actuator. In this study, the high atomic beam, stabilized by oxidation film and organic materials at the material surface, is investigated, and the purified is obtained by removing the oxidation film and pollution layer at the materials. And the unstable surface is obtained, which can be easily joined. In order to use the low temperatures for the joint method, the main subjects are obtained as follows: 1) In the case of the silicon wafer and the silicon wafer and the silicon wafer of alumina sputter film, the specimens can be jointed at 2$0^{\circ}C$, and the joining strength is 5Mpa. 2) The specimens can not always be joined at the room temperatures in the case of the silicon wafer and the silicon wafer of alumina sputter film.

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Design of Single-wafer Wet Etching Bath for Silicon Wafer Etching (실리콘 웨이퍼 습식 식각장치 설계 및 공정개발)

  • Kim, Jae Hwan;Lee, Yongil;Hong, Sang Jeen
    • Journal of the Semiconductor & Display Technology
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    • v.19 no.2
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    • pp.77-81
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    • 2020
  • Silicon wafer etching in micro electro mechanical systems (MEMS) fabrication is challenging to form 3-D structures. Well known Si-wet etch of silicon employs potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH) and sodium hydroxide (NaOH). However, the existing silicon wet etching process has a fatal disadvantage that etching of the back side of the wafer is hard to avoid. In this study, a wet etching bath for 150 mm wafers was designed to prevent back-side etching of silicon wafer, and we demonstrated the optimized process recipe to have anisotropic wet etching of silicon wafer without any damage on the backside. We also presented the design of wet bath for 300 mm wafer processing as a promising process development.

Effects of Forced Self Driving Function in Silicon Wafer Polishing Head on the Planarization of Polished Wafer Surfaces (실리콘 웨이퍼 연마헤드의 강제구동 방식이 웨이퍼 연마 평탄도에 미치는 영향 연구)

  • Kim, Kyoungjin;Park, Joong-Youn
    • Journal of the Semiconductor & Display Technology
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    • v.13 no.1
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    • pp.13-17
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    • 2014
  • Since the semiconductor manufacturing requires the silicon wafers with extraordinary degree of surface flatness, the surface polishing of wafers from ingot cutting is an important process for deciding surface quality of wafers. The present study introduces the development of wafer polishing equipment and, especially, the wafer polishing head that employs the forced self-driving of installed silicon wafer as well as the wax wafer mounting technique. A series of wafer polishing tests have been carried out to investigate the effects of self-driving function in wafer polishing head. The test results for wafer planarization showed that the LLS counts and SBIR of polished wafer surfaces were generally improved by adopting the self-driven polishing head in wafer polishing stations.

Realization of High Q Inductor on Low Resistivity Silicon Wafer using a New and simple Trench Technique (새로운 트랜치 방법을 이용한 저저항 실리콘 기판에서의 High Q 인덕터의 구현)

  • 이홍수;이진효유현규김대용
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.629-632
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    • 1998
  • This paper presents a new and simple technique to realize high Q inductor on low resistivity silicon wafer with 6 $\Omega$.cm. This technique is very compatible with bipolar and CMOS standard silicon process. By forming the deep and narrow trenches on the low resistivity wafer substrate under inductor pattern, oxidizing and filling with undoped polysilicon, the low resistivity silicon wafer acts as high resistivity wafer being suitable for the fabrication of high Q inductor. By using this technique the quality factor (Q) for 8-turn spiral inductor was improved up to max. 10.3 at 2 ㎓ with 3.0 $\mu\textrm{m}$ of metal thickness. The experiment results show that Q on low resistivity silicon wafer with the trench technique have been improved more than 2 times compared to the conventional low resistivity silicon wafer without trenches.

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The Behavior of Intrinsic Bubbles in Silicon Wafer Direct Bonding (실리콘 웨이퍼 직접접합에서 내인성 Bubble의 거동에 관한 연구)

  • Moon, Do-Min;Jeong, Hae-Do
    • Journal of the Korean Society for Precision Engineering
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    • v.16 no.3 s.96
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    • pp.78-83
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    • 1999
  • The bonding interface is dependent on the properties of surfaces prior to SDB(silicon wafer direct bonding). In this paper, we prepared silicon surfaces in several chemical solutions, and annealed bonding wafers which were combined with thermally oxidized wafers and bare silicon wafers in the temperature range of $600{\times}1000^{\circ}C$. After bonding, the bonding interface is investigated by an infrared(IR) topography system which uses the penetrability of infrared through silicon wafer. Using this procedure, we observed intrinsic bubbles at elevated temperatures. So, we verified that these bubbles are related to cleaning and drying conditions, and the interface oxides on silicon wafer reduce the formation of intrinsic bubbles.

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Double treated mixed acidic solution texture for crystalline silicon solar cells

  • Kim, S.C.;Kim, S.Y.;Yi, J.S.
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.02a
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    • pp.323-323
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    • 2010
  • Saw damage of crystalline silicon wafer is unavoidable factor. Usually, alkali treatment for removing the damage has been carried out as the saw damage removal (SDR) process for priming the alkali texture. It usually takes lots of time and energy to remove the sawed damages for solar grade crystalline silicon wafers We implemented two different mixed acidic solution treatments to obtain the improved surface structure of silicon wafer without much sacrifice of the silicon wafer thickness. At the first step, the silicon wafer was dipped into the mixed acidic solution of $HF:HNO_3$=1:2 ration for polished surface and at the second step, it was dipped into the diluted mixed acidic solution of $HF:HNO_3:H_2O$=7:3:10 ratio for porous structure. This double treatment to the silicon wafer brought lower reflectance (25% to 6%) and longer carrier lifetime ($0.15\;{\mu}s$ to $0.39\;{\mu}s$) comparing to the bare poly-crystalline silicon wafer. With optimizing the concentration ratio and the dilution ratio, we can not only effectively substitute the time consuming process of SDR to some extent but also skip plasma enhanced chemical vapor deposition (PECVD) process. Moreover, to conduct alkali texture for pyramidal structure on silicon wafer surface, we can use only nitric acid rich solution of the mixed acidic solution treatment instead of implementing SDR.

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Fabrication of MEMS Devices Using SOI(Silicon-On-Insulator)-Micromachining Technology (SOI(Silicon-On-Insulator)- Micromachining 기술을 이용한 MEMS 소자의 제작)

  • 주병권;하주환;서상원;최승우;최우범
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.07a
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    • pp.874-877
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    • 2001
  • SOI(Silicon-On-Insulator) technology is proposed as an alternative to bulk silicon for MEMS(Micro Electro Mechanical System) manufacturing. In this paper, we fabricated the SOI wafer with uniform active layer thickness by silicon direct bonding and mechanical polishing processes. Specially-designed electrostatic bonding system is introduced which is available for vacuum packaging and silicon-glass wafer bonding for SOG(Silicon On Glass) wafer. We demonstrated thermopile sensor and RF resonator using the SOI wafer, which has the merits of simple process and uniform membrane fabrication.

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A Study on the Contaminants Precision Cleaning of Etched Silicon Wafer by Ozone/UV (오존/자외선에 의한 실리콘 웨이퍼의 정밀세정에 관한 연구)

  • Park, H.M.;Lee, C.H.;Chun, B.J.;Yoon, B.H.;Lim, C.H.;Song, H.J.;Kim, Y.H.;Lee, K.S.
    • Proceedings of the KIEE Conference
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    • 2004.07c
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    • pp.1820-1822
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    • 2004
  • In this study, major research fields are classified as ozone generation system for dry cleaning wafer of etched silicon wafer, dry cleaning process of etched silicon wafer which includes SEM analysis and ESCA analysis. The following results are deduced from each experiment and analysis. The magnitudes of carbon and silicon were similar to the survey spectrum of silicon wafer which does not cleaning, but magnitude of oxygen was much bigger Because UV light activates oxygen molecules in the oxide film on the silicon wafer.

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The annihilation of the flow pattern defects in CZ-silicon crystal by high temperature heat treatment (고온 열처리에 의한 결정결함의 재용해)

  • 서지욱;김영관
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.11 no.3
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    • pp.89-95
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    • 2001
  • The CZ-silicon crystal was annealed at $1350^{\circ}C$ to dissolve the vacancy type grown-in defects. A this temperature, the equilibrium concentration of the oxygen in the silicon crystal is around $1.7{\times}10^{18}$ which induces the oxygen undersaturation in the silicon crystal. This situation results in the faster dissolution of the grown-in defects in the bulk of the silicon wafer than near the surface. This indicates the possibility that the presence of the higher concentration of silicon interstitial hinders the dissolution of the grown-in defects, which were known to compose of the vacancy clusters with surrounding silicon oxide film. This expectation was confirmed by the observation that the slower dissolution of the grown-in defects near the surface of the silicon wafer in the oxygen atmosphere than in the argon atmosphere. This result is quite opposite to the previous argument hat presence of the excess silicon interstitial leads to faster dissolution of the vacancy type defects.

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