• 한국생산제조학회지
• /
• 제6권4호
• /
• pp.34-38
• /
• 1997

This paper presents a joining method by using the silicon wafer in order to apply to joint to the 3-dimensional structures of semiconductor device, high-speed , high integration, micro machine, silicon integrated sensor, and actuator. In this study, the high atomic beam, stabilized by oxidation film and organic materials at the material surface, is investigated, and the purified is obtained by removing the oxidation film and pollution layer at the materials. And the unstable surface is obtained, which can be easily joined. In order to use the low temperatures for the joint method, the main subjects are obtained as follows: 1) In the case of the silicon wafer and the silicon wafer and the silicon wafer of alumina sputter film, the specimens can be jointed at 2$0^{\circ}C$, and the joining strength is 5Mpa. 2) The specimens can not always be joined at the room temperatures in the case of the silicon wafer and the silicon wafer of alumina sputter film.

• 반도체디스플레이기술학회지
• /
• 제19권2호
• /
• pp.77-81
• /
• 2020

Silicon wafer etching in micro electro mechanical systems (MEMS) fabrication is challenging to form 3-D structures. Well known Si-wet etch of silicon employs potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH) and sodium hydroxide (NaOH). However, the existing silicon wet etching process has a fatal disadvantage that etching of the back side of the wafer is hard to avoid. In this study, a wet etching bath for 150 mm wafers was designed to prevent back-side etching of silicon wafer, and we demonstrated the optimized process recipe to have anisotropic wet etching of silicon wafer without any damage on the backside. We also presented the design of wet bath for 300 mm wafer processing as a promising process development.

• 반도체디스플레이기술학회지
• /
• 제13권1호
• /
• pp.13-17
• /
• 2014

Since the semiconductor manufacturing requires the silicon wafers with extraordinary degree of surface flatness, the surface polishing of wafers from ingot cutting is an important process for deciding surface quality of wafers. The present study introduces the development of wafer polishing equipment and, especially, the wafer polishing head that employs the forced self-driving of installed silicon wafer as well as the wax wafer mounting technique. A series of wafer polishing tests have been carried out to investigate the effects of self-driving function in wafer polishing head. The test results for wafer planarization showed that the LLS counts and SBIR of polished wafer surfaces were generally improved by adopting the self-driven polishing head in wafer polishing stations.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1998년도 추계종합학술대회 논문집
• /
• pp.629-632
• /
• 1998

This paper presents a new and simple technique to realize high Q inductor on low resistivity silicon wafer with 6 $\Omega$.cm. This technique is very compatible with bipolar and CMOS standard silicon process. By forming the deep and narrow trenches on the low resistivity wafer substrate under inductor pattern, oxidizing and filling with undoped polysilicon, the low resistivity silicon wafer acts as high resistivity wafer being suitable for the fabrication of high Q inductor. By using this technique the quality factor (Q) for 8-turn spiral inductor was improved up to max. 10.3 at 2 ㎓ with 3.0 $\mu\textrm{m}$ of metal thickness. The experiment results show that Q on low resistivity silicon wafer with the trench technique have been improved more than 2 times compared to the conventional low resistivity silicon wafer without trenches.

• 한국정밀공학회지
• /
• 제16권3호통권96호
• /
• pp.78-83
• /
• 1999

The bonding interface is dependent on the properties of surfaces prior to SDB(silicon wafer direct bonding). In this paper, we prepared silicon surfaces in several chemical solutions, and annealed bonding wafers which were combined with thermally oxidized wafers and bare silicon wafers in the temperature range of $600{\times}1000^{\circ}C$. After bonding, the bonding interface is investigated by an infrared(IR) topography system which uses the penetrability of infrared through silicon wafer. Using this procedure, we observed intrinsic bubbles at elevated temperatures. So, we verified that these bubbles are related to cleaning and drying conditions, and the interface oxides on silicon wafer reduce the formation of intrinsic bubbles.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2009년도 제38회 동계학술대회 초록집
• /
• pp.323-323
• /
• 2010

Saw damage of crystalline silicon wafer is unavoidable factor. Usually, alkali treatment for removing the damage has been carried out as the saw damage removal (SDR) process for priming the alkali texture. It usually takes lots of time and energy to remove the sawed damages for solar grade crystalline silicon wafers We implemented two different mixed acidic solution treatments to obtain the improved surface structure of silicon wafer without much sacrifice of the silicon wafer thickness. At the first step, the silicon wafer was dipped into the mixed acidic solution of $HF:HNO_3$=1:2 ration for polished surface and at the second step, it was dipped into the diluted mixed acidic solution of $HF:HNO_3:H_2O$=7:3:10 ratio for porous structure. This double treatment to the silicon wafer brought lower reflectance (25% to 6%) and longer carrier lifetime ($0.15\;{\mu}s$ to $0.39\;{\mu}s$) comparing to the bare poly-crystalline silicon wafer. With optimizing the concentration ratio and the dilution ratio, we can not only effectively substitute the time consuming process of SDR to some extent but also skip plasma enhanced chemical vapor deposition (PECVD) process. Moreover, to conduct alkali texture for pyramidal structure on silicon wafer surface, we can use only nitric acid rich solution of the mixed acidic solution treatment instead of implementing SDR.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2001년도 하계학술대회 논문집
• /
• pp.874-877
• /
• 2001

SOI(Silicon-On-Insulator) technology is proposed as an alternative to bulk silicon for MEMS(Micro Electro Mechanical System) manufacturing. In this paper, we fabricated the SOI wafer with uniform active layer thickness by silicon direct bonding and mechanical polishing processes. Specially-designed electrostatic bonding system is introduced which is available for vacuum packaging and silicon-glass wafer bonding for SOG(Silicon On Glass) wafer. We demonstrated thermopile sensor and RF resonator using the SOI wafer, which has the merits of simple process and uniform membrane fabrication.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2004년도 하계학술대회 논문집 C
• /
• pp.1820-1822
• /
• 2004

In this study, major research fields are classified as ozone generation system for dry cleaning wafer of etched silicon wafer, dry cleaning process of etched silicon wafer which includes SEM analysis and ESCA analysis. The following results are deduced from each experiment and analysis. The magnitudes of carbon and silicon were similar to the survey spectrum of silicon wafer which does not cleaning, but magnitude of oxygen was much bigger Because UV light activates oxygen molecules in the oxide film on the silicon wafer.

• 한국결정성장학회지
• /
• 제11권3호
• /
• pp.89-95
• /
• 2001

규소 결정의 용융 온도 근처인 $1350^{\circ}C$에서 Ar과 $O_{2}$gas를 이용하여 규소 wafer의 열처리시 vacancy ty[e 결함의 거동에 대해 알아보았다. 이 열처리에서는 wafer의 표면보다 wafer내부에서 결함의 용해속도가 매우 높음을 확인하였다. 이는 $1350^{\circ}C$에서는 규소내의 평형산소농도가 대부분의 CZ silicon에서의 산소농도보다 높아 산소의 understaturation현상과 silicon interstitial농도의 영향에 기인된 것으로 예상된다. 열처리 분위기의 영향을 알아보기 위하여 Ar과 $O_{2}$ 분위기에서 열처리한 결과 vacancy type 결함의 용해속도는 wafer의 내부에서는 차이가 없었고, wafer의 표면에서는 Ar이 $O_{2}$의 경우보다 결함의 용해속도가 높았다. $O_{2}$의 경우에는 표면산화막 성장시 유입된 silicon interstitial의 농도가 높아 결함의 용해속도가 떨어지는 것으로 판단된다. 이는 기존 연구에서 예상된 silicon interstitial이 vacancy cluster로 알려진 결정결함의 제거에 기여한다는 예상과는 상반된다. 본 연구의 결과 silicon interstitial의 존재는 void외부 산화막의 용해속도를 늦추어 결함 용해속도를 떨어뜨리는 것으로 예상된다.

• 한국신재생에너지학회:학술대회논문집
• /
• 한국신재생에너지학회 2007년도 추계학술대회 논문집
• /
• pp.232-232
• /
• 2007