• Title/Summary/Keyword: Silicon wafer

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Study on Analysis of Optical Deflection of Laser Scattering Based on Rayleigh Criterion for Crystalline Silicon Wafer in Solar Cell (태양전지용 결정질 실리콘 웨이퍼에서의 레일리기준 기반 레이저산란의 광편향 분석에 관한 연구)

  • Kim, Gyung-Bum
    • Journal of the Semiconductor & Display Technology
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    • v.9 no.4
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    • pp.31-37
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    • 2010
  • In this paper, optical deflection of laser scattering has been investigated based on Rayleigh criterion for crystalline silicon wafer in solar cell. A laser scattering mechanism is newly designed using light scattering properties in silicon wafer. Intensity distributions of laser scattering are different, depending on the incident angle of laser computed from Rayleigh criterion. In case of the incident angle satisfied with the criterion, they are asymmetric. Also, their specular reflection angle is shifted to unpredicted ones. These phenomena are in accordance with previous theories of laser scattering. The optical deflection of laser scattering is experimentally identified with the designed laser scattering mechanism. Its mathematical model is presented from the geometric relationship of laser scattering. It is shown that the optical deflection of laser scattering agree with the presented model, exclusive of grazing angles which is satisfied with Rayleigh criterion.

A Study on Performance Evaluation of Typical Classification Techniques for Micro-cracks of Silicon Wafer (실리콘 웨이퍼 마이크로크랙을 위한 대표적 분류 기술의 성능 평가에 관한 연구)

  • Kim, Sang Yeon;Kim, Gyung Bum
    • Journal of the Semiconductor & Display Technology
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    • v.15 no.3
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    • pp.6-11
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    • 2016
  • Silicon wafer is one of main materials in solar cell. Micro-cracks in silicon wafer are one of reasons to decrease efficiency of energy transformation. They couldn't be observed by human eye. Also, their shape is not only various but also complicated. Accordingly, their shape classification is absolutely needed for manufacturing process quality and its feedback. The performance of typical classification techniques which is principal component analysis(PCA), neural network, fusion model to integrate PCA with neural network, and support vector machine(SVM), are evaluated using pattern features of micro-cracks. As a result, it has been confirmed that the SVM gives good results in micro-crack classification.

A Study on Ultraprecision Dicing Machining of Silicon Wafer (실리콘 웨이퍼의 초정밀 절단가공에 관한 연구)

  • 김성철
    • Proceedings of the Korean Society of Machine Tool Engineers Conference
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    • 1999.10a
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    • pp.502-506
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    • 1999
  • Recently, the miniature of electric products such as notebook, cellular-phone etc. is apparently appeared, due to the smaller size of the semiconductor chips. As the size of chip gets smaller, the circuit could be easily damaged by the slightest influence, so it is important to control the chipping generation in the process of dicing. This paper deals with chipping of the silicon wafer dicing. The relationships between the dicing force and the wafer chipping are investigated. It is confirmed that the wafer chipping increases as the dicing force increases.

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Micro-crack Detection in Silicon Solar Wafer through Optimal Parameter Selection in Anisotropic Diffusion Filter (비등방 확산 필터의 최적조건 선정을 통한 태양전지 실리콘 웨이퍼의 마이크로 크랙 검출)

  • Seo, Hyoung Jun;Kim, Gyung Bum
    • Journal of the Semiconductor & Display Technology
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    • v.13 no.3
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    • pp.61-67
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    • 2014
  • Micro-cracks in crystalline silicon wafer often result in wafer breakage in solar wafer manufacturing, and also their existence may lead to electrical failure in post fabrication inspection. Therefore, the reliable detection of micro-cracks is of importance in the photovoltaic industry. In this paper, an experimental method to select optimal parameters in anisotropic diffusion filter is proposed. It can reliably detect micro-cracks by the distinct extension of boundary as well as noise reduction in near-infrared image patterns of micro-cracks. Its performance is verified by experiments of several type cracks machined.

Processing and Characterization of a Direct Bonded SOI using SiO$_2$ Thin Film (SiO$_2$ 박막을 이용한 SOI 직접접합공정 및 특성)

  • 유연혁;최두진
    • Journal of the Korean Ceramic Society
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    • v.36 no.8
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    • pp.863-870
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    • 1999
  • SOI(silicon on insulafor) was fabricated through the direct bonding using (100) Si wafer and 4$^{\circ}$off (100) Si wafer to investigate the stacking faults in silicon at the Si/SiO2 oxidized and bonded interface. The treatment time of wafer surface using MSC-1 solution was varied in order to observe the effect of cleaning on bonding characteristics. As the MSC-1 treating time increased surface hydrophilicity was saturated and surface microroughness increased. A comparison of surface hydrophilicity and microroughness with MSC-1 treating time indicates that optimum surface modified condition for time was immersed in MSC-1 for 2 min. The SOI structure directly bonded using (100) Si wafer and 4$^{\circ}$off (100) Si wafer at the room temperature were annealed at 110$0^{\circ}C$ for 30 min. Then the stacking faults at the bonding and oxidation interface were examined after the debonding. The results show that there were anomalies in the gettering of the stacking faults at the bonded region.

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A study on the Digital contents for Estimated Thickness Algorithm of Silicon wafer (실리콘웨이퍼 평탄도 추정 알고리즘을 위한 디지털 컨덴츠에 관한 연구)

  • Song Eun-Jee
    • Journal of Digital Contents Society
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    • v.5 no.4
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    • pp.251-256
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    • 2004
  • The flatness of a silicon wafer concerned with ULSI chip is one of the most critical parameters ensuring high yield of wafers. That is necessary to constitute the circuit with high quality for he surface of silicon wafer, which comes to be base to make the direct circuit of the semiconductor, Flatness, therefore, is the most important factor to guarantee it wafer with high quality. The process of polishing is one of the most crucial production line among 10 processing stages to change the rough surface into the flatnees with best quality. Currently at this process, it is general for an engineer in charge to observe, judge and control the model of wafer from the monitor of measuring equipment with his/her own eyes to enhance the degree of flatness. This, however, is quite a troublesome job for someone has to check of process by one's physical experience. The purpose of this study is to approach the model of wafer with digital contents and to apply the result of the research for an algorithm which enables to control the polishing process by means of measuring the degree of flatness automatically, not by person, but by system. In addition, this paper shows that this algorithm proposed for the whole wafer flatness enables to draw an estimated algorithm which is for the thickness of sites to measure the degree of flatness for each site of wafer.

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A Three-Dimensional CFD Study on the Air Flow Characteristics in a Wax Spin Coater for Silicon Wafer Manufacturing (실리콘 웨이퍼 생산공정용 왁스 스핀코팅장치 내 기류 특성에 대한 3차원 전산유동해석)

  • Kim, Yong-Ki;Kim, Dong-Joo;Umarov, Alisher;Kim, Kyoung-Jin;Park, Jun-Young
    • Journal of the Korean Society of Manufacturing Process Engineers
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    • v.10 no.6
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    • pp.146-151
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    • 2011
  • Wax spin coating is a part of several wafer handling processes in the silicon wafer polishing station. It is important to ensure the wax layer free of contamination to achieve the high degree of planarization on wafers after wafer polishing. Three-dimensional air flow characteristics in a wax spin coater are numerically investigated using computational fluid dynamics techniques. When the bottom of the wax spin coater is closed, there exists a significant recirculation zone over the rotating ceramic block. This recirculation zone can be the source of wax layer contamination at any rotational speed and should be avoided to maintain high wafer polishing quality. Thus, four air suction ducts are installed at the bottom of the wax spin coater in order to control the air flow pattern over the ceramic block. Present computational results show that the air suction from the bottom is quite an effective method to remove or minimize the recirculation zone over the ceramic block and the wax coating layer.

The Gettering Effect of Boron Doped n-type Monocrystalline Silicon Wafer by In-situ Wet and Dry Oxidation

  • Jo, Yeong-Jun;Yun, Ji-Su;Jang, Hyo-Sik
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.08a
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    • pp.429-429
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    • 2012
  • To investigate the gettering effect of B-doped n-type monocrystalline silicon wafer, we made the p-n junction by diffusing boron into n-type monocrystalline Si substrate and then oxidized the boron doped n-type monocrystalline silicon wafer by in-situ wet and dry oxidation. After oxidation, the minority carrier lifetime was measured by using microwave photoconductance and the sheet resistance by 4-point probe, respectively. The junction depth was analyzed by Secondary Ion Mass Spectrometry (SIMS). Boron diffusion reduced the metal impurities in the bulk of silicon wafer and increased the minority carrier lifetime. In the case of wet oxidation, the sheet resistance value of ${\sim}46{\Omega}/{\Box}$ was obtained at $900^{\circ}C$, depostion time 50 min, and drive-in time 10 min. Uniformity was ~7% at $925^{\circ}C$, deposition time 30 min, and drive-in time 10 min. Finally, the minority carrier lifetime was shown to be increased from $3.3{\mu}s$ for bare wafer to $21.6{\mu}s$ for $900^{\circ}C$, deposition 40 min, and drive-in 10 min condition. In the case of dry oxidation, for the condition of 50 min deposition, 10 min drive-in, and O2 flow of 2000 SCCM, the minority carrier lifetime of 16.3us, the sheet resistance of ${\sim}48{\Omega}/{\Box}$, and uniformity of 2% were measured.

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