• 제목/요약/키워드: Single-bit Feedback

검색결과 29건 처리시간 0.024초

A Study on Single-bit Feedback Multi-bit Sigma Delta A/D converter for improving nonlinearity

  • Kim, Hwa-Young;Ryu, Jang-Woo;Jung, Min-Chul;Sung, Man-Young
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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    • pp.57-60
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    • 2004
  • This paper presents multibit Sigma-Delta ADC using Leslie-Singh Structure to Improve nonlinearity of feedback loop. 4-bit flash ADC for multibit Quantization in Sigma Delta modulator offers the following advantages such as lower quantization noise, more accurate white-noise level and more stability over single quantization. For the feedback paths consisting of DAC, the DAC element should have a high matching requirement in order to maintain the linearity performance which can be obtained by the modulator with a multibit quantizer. Thus a Sigma-Delta ADC usually adds the dynamic element matching digital circuit within feedback loop. It occurs complexity of Sigma-Delta Circuit and increase of power dissipation. In this paper using the Leslie-Singh Structure for improving nonliearity of ADC. This structure operate at low oversampling ratio but is difficult to achieve high resolution. So in this paper propose improving loop filter for single-bit feedback multi-bit quantization Sigma-Delta ADC. It obtained 94.3dB signal to noise ratio over 615kHz bandwidth, and 62mW power dissipation at a sampling frequency of 19.6MHz. This Sigma Delta ADC is fabricated in 0.25um CMOS technology with 2.5V supply voltage.

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X-ray 이미지 센서용 싱글 픽셀 포톤 카운터 설계 (A Design of Single Pixel Photon Counter for Digital X-ray Image Sensor)

  • 백승면;김태호;강형근;전성채;진승오;허영;하판봉;박무훈;김영희
    • 한국정보통신학회논문지
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    • 제11권2호
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    • pp.322-329
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    • 2007
  • 본 논문에서는 디지털 의료 영상 및 진단 분야 그리고 산업용으로도 활용 가능한 싱글 포톤 계수형 영상센서를 $0.18{\mu}m$ triple-well CMOS(Complementary Metal Oxide Semiconductor) 공정을 사용하여 설계하였다. 설계된 Readout 칩용 싱글 픽셀은 디지털 X-ray 이미지 센서모듈을 간단화 하기 위해 단일 전원전압을 사용하였으며, Preamplifier의 출력 전압인 signal voltage(${\Delta}Vs$)를 크게 하기 위해 Folded Cascode CMOS OP amp를 이용한 Preamplifier를 설계하였으며, 기존의 Readout 칩 외부에서 인가하던 threshold voltage를 Readout 칩 내부에서 생성해 줄 수 있도록 Externally Tunable Threshold Voltage Generator 회로를 새롭게 제안하였다. 그리고, Photo Diode에서 발생하는 Dark Current Noise를 제거하기 위한 Dark Current Compensation 회로를 제안하였으며, 고속 counting이 가능하고, layout 면적이 작은 15bit LFSR(Linear Feedback Shift Resister) Counter를 설계하였다.

Real-time implementation of distributed beamforming for simultaneous wireless information and power transfer in interference channels

  • Hong, Yong-Gi;Hwang, SeongJun;Seo, Jiho;Lee, Jonghyeok;Park, Jaehyun
    • ETRI Journal
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    • 제43권3호
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    • pp.389-399
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    • 2021
  • In this paper, we propose one-bit feedback-based distributed beamforming (DBF) techniques for simultaneous wireless information and power transfer in interference channels where the information transfer and power transfer networks coexist in the same frequency spectrum band. In a power transfer network, multiple distributed energy transmission nodes transmit their energy signals to a single energy receiving node capable of harvesting wireless radio frequency energy. Here, by considering the Internet-of-Things sensor network, the energy harvesting/information decoding receivers (ERx/IRx) can report their status (which may include the received signal strength, interference, and channel state information) through one-bit feedback channels. To maximize the amount of energy transferred to the ERx and simultaneously minimize the interference to the IRx, we developed a DBF technique based on one-bit feedback from the ERx/IRx without sharing the information among distributed transmit nodes. Finally, the proposed DBF algorithm in the interference channel is verified through the simulations and also implemented in real time by using GNU radio and universal software radio peripheral.

등가회로 모델에 의한 레이저다이오드의 누설전류 해석 (Analysis of Leakage Current of a Laser Diode by Equivalent Circuit Model)

  • 최영규;김기래
    • 한국정보통신학회논문지
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    • 제11권2호
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    • pp.330-336
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    • 2007
  • 본 논문에서는 디지털 의료 영상 및 진단 분야 그리고 산업용으로도 활용 가능한 싱글 포톤 계수형 영상센서를 $0.18{\mu}m$ triple-well CMOS(Complementary Metal Oxide Semiconductor) 공정을 사용하여 설계하였다. 설계된 Readout 칩용 싱글 픽셀은 디지털 X-ray 이미지 센서모듈을 간단화 하기 위해 단일 전원전압을 사용하였으며, Preamplifier의 출력 전압인 signal voltage(${\Delta}Vs$)를 크게 하기 위해 Folded Cascode CMOS OP amp를 이용한 Preamplifier를 설계하였으며, 기존의 Readout 칩 외부에서 인가하던 threshold voltage를 Readout 칩 내부에서 생성해 줄 수 있도록 Externally Tunable Threshold Voltage Generator 회로를 새롭게 제안하였다. 그리고, Photo Diode에서 발생하는 Dark Current Noise를 제거하기 위한 Dark Current Compensation 회로를 제안하였으며, 고속 counting이 가능하고, layout 면적이 작은 15bit LFSR(Linear Feedback Shift Resister) Counter를 설계하였다.

OFDM 무선 LAN 시스템에 적용할 FFT/IFFT 프로세서의 설계 (Desing of FFT/IFFT processor that is applied to OFDM wireless LAN system)

  • 권병천;고성찬
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2002년도 하계종합학술대회 논문집(1)
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    • pp.5-8
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    • 2002
  • In this paper, we are designed and verified a FFT/IFFT processor that is possible from the wireless LAN environment which is adopted international standard of the IEEE802.11a. The proposed architecture of the FFT/IFFT has Radix-2 64point SDF(single-path delay feedback) Pipeline technique and DIF(Decimation in Frequenct) structure. The FFT/IFFT processor has each 8 bit complex input-output and 6 bit Twiddle factor. we used Max-PlusII for simulation and can see that processor is properly operated

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비선형 부하에서 커패시터 전류 궤환을 통한 고성능 UPS 설계 (A Design of a High Performance UPS with Capacitor Current Feedback for Nonlinear Loads)

  • 이우철;이택기
    • 조명전기설비학회논문지
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    • 제26권5호
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    • pp.71-78
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    • 2012
  • This paper presents a digital control solution to process capacitor current feedback of high performance single-phase UPS for non-linear loads. In all UPS the goal is to maintain the desired output voltage waveform and RMS value over all unknown load conditions and transient response. The proposed UPS uses instantaneous load voltage and filter capacitor current feedback, which is based on the double regulation loop such as the outer voltage control loop and inner current control loop. The proposed DSP-based digital-controlled PWM inverter system has fast dynamic response and low total harmonic distortion (THD) for nonlinear load. The control system was implemented on a 32bit Floating-point DSP controller TMS320C32 and tested on a 5[KVA] IGBT based inverter switching at 11[Khz]. The validity of the proposed scheme is investigated through simulation and experimental results.

ON A CHARACTERIZATION OF T-FUNCTIONS WITH ONE CYCLE PROPERTY

  • Rhee, Min Surp
    • 충청수학회지
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    • 제21권2호
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    • pp.259-268
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    • 2008
  • To the design of secret key, there are two types of basic approaches called the tame approach and the wild approach. In the tame approach we try to use only simple primitives such as linear feedback shift registers and to prove mathematical theorems about their cryptographic properties. In the wild approach we try to use crazy compositions of operations which mix a variety of domains in a nonlinear and nonalgebraic way. There are several papers which try to bridge this gap by considering semi-wild constructions. A T-function on n-bit words plays an important role in semi-wild constructions. In this paper we study the invertibility and the period of some T-functions. Especially we characterize some polynomials which has a single cycle property.

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On the Performance of Incremental Opportunistic Relaying with Differential Modulation over Rayleigh Fading Channels

  • 보 웬 옥 바오;공형윤
    • 한국통신학회논문지
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    • 제35권7A호
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    • pp.731-742
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    • 2010
  • We propose an incremental relaying protocol in conjunction with opportunistic communication for differential modulation with an aim to make efficient use of the degrees of freedom of the channels by exploiting a imited feedback signal from the destination. In particular, whenever the direct link from the source to the destination is not favorable to decoding, the destination will request the help from the opportunistic relay (if any). The performance of the proposed system is derived in terms of average bit error probability and achievable spectral efficiency. The analytic results show that the system assisted by the opportunistic relaying can achieve full diversity at low SNR regime and exhibits a 30㏈ gain relative to direct transmission, assuming single-antenna terminals. We also determine the effect of power allocation on the bit error probability BEP) performance of our relaying scheme. We conclude with a discussion on the relationship between the given thresholds and channel resource savings. Monte-Carlo simulations are performed to verify the analysis.

Distributed beamforming with one-bit feedback and clustering for multi-node wireless energy transfer

  • Lee, Jonghyeok;Hwang, SeongJun;Hong, Yong-gi;Park, Jaehyun;Byun, Woo-Jin
    • ETRI Journal
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    • 제43권2호
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    • pp.221-231
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    • 2021
  • To resolve energy depletion issues in massive Internet of Things sensor networks, we developed a set of distributed energy beamforming methods with one-bit feedback and clustering for multi-node wireless energy transfer, where multiple singleantenna distributed energy transmitters (Txs) transfer their energy to multiple nodes wirelessly. Unlike previous works focusing on distributed information beamforming using a single energy receiver (Rx) node, we developed a distributed energy beamforming method for multiple Rx nodes. Additionally, we propose two clustering methods in which each Tx node chooses a suitable Rx node. Furthermore, we propose a fast distributed beamforming method based on Tx sub-clustering. Through computer simulations, we demonstrate that the proposed distributed beamforming method makes it possible to transfer wireless energy to massive numbers of sensors effectively and rapidly with small implementation complexity. We also analyze the energy harvesting outage probability of the proposed beamforming method, which provides insights into the design of wireless energy transfer networks with distributed beamforming.

Delayed LMS와 Redundant Binary 복소수 필터구조를 이용한 파이프라인 적응 결정귀환 등화기 설계 (A Design of Pipelined Adaptive Decision-Feedback Equalized using Delayed LMS and Redundant Binary Complex Filter Structure)

  • 안병규;이종남;신경욱
    • 대한전자공학회논문지SD
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    • 제37권12호
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    • pp.60-69
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    • 2000
  • 광대역 무선 디지털 통신 시스템용 파이프라인 적응 결정귀환 등화기(pipelined adaptive decision-feedback equalizer; PADFE)를 0,25-${\mu}m$ CMOS 공정을 사용하여 full custom 단일 칩으로 설계하였다. ADFE의 동작속도를 향상시키기 위해 DLMS(delayed least-mean-square)을 적용한 2-stage 파이프라인 구조로 설계하였다. PADFE의 필터와 계수갱신 블록 등 모든 연산을 redundant binary(RB) 수치계로 처리하였으며, 2의 보수 수치계를 사용하는 기존의 방식에 비해 연산량의 감소와 동작속도의 향상이 얻어졌으며, 또한 전체적인 구조의 단순화에 의해 VLSI 구현이 용이하다는 장점을 갖는다. COSSAP을 이용한 알고리듬 레벨 시뮬레이션을 통해 파이프라인 stage 수, 필터 tap 수, 계수 및 내부 비트 수 등의 설계 파라메터 결정과 bit error rate(BER), 수렴속도 등을 분석하였다. 설계된 PADFE는 약 205,000개의 트랜지스터로 구성되며, 코어의 면적은 41.96\times1.35-mm^2$이다. 시뮬레이션 결과, 2.5-V 전원전압에서 200-MHz의 클록 주파수로 동작 가능할 것으로 예상되며, 평균 전력소모는 약 890-mW로 예측되었다. 제작된 칩의 테스트 결과로부터 기능이 정상적으로 동작함을 확인하였다.

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