• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.381-384
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• 1999

In this paper, we addressed the problem of reducing the switching activity in pipeline datapath and proposed a solution. clock-gating method is a kind of practical technique for reducing switching activity in finite state machine. But, in the case that the target gated function unit has a pipeline structure, there is some spurious switching activity on each stage register group. This occur in early stage of every function enable cycle. In this paper we proposed a method to solve this problem. This method generates the enable signal to each pipeline stage to gate the clock feeding register group. Experimental results showed effective reduction of dynamic powers in pipeline circuits.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.166-171
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• 2003

In this paper, we propose a minimal power data path allocation algorithm for low power circuit design. The proposed algorithm minimizes switching activity for input variables in scheduled CDFG. Allocations are further divided into the tasks of register allocation and module allocation. The register allocation algorithm execute that it eliminate spurious switching activity in functional unit and minimize the numbers of multiplexer. Also, resource allocation method selects a sequence of operations for a module such that the switching activity is reduced. Therefore, the algorithm executes to minimize the switching activity of input values, sequence of operations and number of multiplexer. Experimental results using benchmarks show that power is reduction effect from 13% to 17% power consumption, when compared with the Genesis-lp high-level synthesis system.

• The KIPS Transactions:PartA
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• v.12A no.1 s.91
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• pp.1-6
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• 2005

This paper presents a new algorithm on low power survivor path memory implementation of the trace-back systolic array Viterbi algorithm. A novel idea is to reuse the already-generated trace-back routes to reduce the number of trace-back operations. And the spurious switching activity of the trace-back unit is reduced by making use of a clock gating method. Using the SYNOPSYS power estimation tool, DesignPower, our experimental result shows the average $40{\%}$ power reduction and $23{\%}$ area increase against the trace-back unit introduced in [1].

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10C
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• pp.1042-1050
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• 2007

This paper describes the system which automatically generates power-minimized embedded cores from MDL descriptions. An automatic generation system is constructed which generated embedded cores which consumes less power for application programs. From the usage information on pipeline stages for each instruction, the proposed system generates embedded cores with the capability of detecting/resolving pipeline hazards. The generated cores are configured such that the power consumption is minimized. The proposed system has been tested by generating HDL codes for ARM9, MIPS R3000 architectures. Experimental results show functional accuracy of the generated cores, and show that power reduction of $20%{\sim}40%$ has been observed for benchmark programs.