• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.523-524
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• 2006

Successive approximation A/D converters have an advantage of small chip area and simple algorithm. We propose an improved non-redundant successive approximation register (SAR) which can be incorporated in successive approximation A/D converters. The proposed SAR validates the preset state as the $1^{st}$ reference voltage to the comparator. Two redundant clock cycles in the typical design could be eliminated in the proposed A/D converter.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.483-485
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• 2010

A 200kS/s 10-bit successive approximation(SA) ADC with a rail-to-rail input range is proposed. The proposed SA ADC consists of DAC, comparator, and successive approximation register(SAR) logic. The folded-type capacitor DAC with the boosted NMOS switches is used to reduce the power consumption and chip area. Also, the time-domain comparator which uses a fully differential voltage-to-time converter improves the PSRR and CMRR. The SAR logic uses the flip-flop with a half valid window, it results in the reduction of the power consumption and chip area. The proposed SA ADC is designed by using a $0.18{\mu}m$ CMOS process with 1V supply.

• Journal of Sensor Science and Technology
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• v.28 no.4
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• pp.240-245
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• 2019

Phase interpolation is widely adopted in frequency synthesizers and clock-and-data recovery systems to produce an intermediate phase from two existing phases. The intermediate phase is typically generated by combining two input phases with different weights. Unfortunately, this results in non-uniform phase steps. Alternatively, the intermediate phase can be generated by successive approximation, where the interpolated phase at each approximation stage is obtained using the same weight for the two intermediate phases. As a proof of concept, this study presents a 2-GHz 8-bit successive approximation digital-to-phase converter that is designed using 65-nm CMOS technology. The converter receives an 8-phase clock signal as input, and the most significant bit (MSB) section selects four phases to create two sinusoidal waveforms using a harmonic rejection filter. The remaining least significant bit (LSB) section applies the successive approximation to generate the required intermediate phase. Monte-Carlo simulations show that the proposed converter exhibits 0.46-LSB integral nonlinearity and 0.31-LSB differential nonlinearity with a power consumption of 3.12 mW from a 1.2-V supply voltage.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1986.10a
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• pp.68-71
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• 1986

A new circuit configuration for charge-balancing successive approximation Analog-to-Digital converters is described. This consists of a improved successive approximation register(SAR) and a weighted capacitor Digital-to-Analog converter (WCDAC). Due to the inherent conversion property of the WCDAC, the A/D converter using the WCDAC can be simply implemented by successive approximation conversion method, and 4bit monotonicity conversion with differential nonlinearity less 1/2LSB is completed in 80 US.

• 제어로봇시스템학회:학술대회논문집
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• 1987.10a
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• pp.847-850
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• 1987

In this paper a new method to correct the differential non-linearity(D NL) error for a successive approximation is proposed. The DNL of ADC is very important characteristic in the field of radiation pulse height analysis or measurement of probability density function. The results of computer simulations are shown to demonstrate the feasibility of the proposed correction method.

• Journal of applied mathematics & informatics
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• v.28 no.3_4
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• pp.739-751
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• 2010

This article presents the result on existence, uniqueness and stability of mild solution of impulsive stochastic partial neutral functional differential equations under sufficient condition. The results are obtained by using the method of successive approximation.

• 제어로봇시스템학회:학술대회논문집
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• 1989.10a
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• pp.943-946
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• 1989

The channel irregularity of Successive Approximation ADC is very large in comparison with other type of ADCs. This characteristic makes it impossible to apply the Successive Approximation ADC to the field of radiation pulse height analysis or the measurement of probability density function. In this paper, an analysis of differential non-linearity of this ADC-is presented. It is made clear that the small deviation of resistance causes very large differential non-linearity.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.68 no.1
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• pp.90-97
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• 2019

The charge redistribution digital-to-analog converter(CR-DAC) is often used for successive approximation register analog-to-digital converter(SAR ADC) that requiring low power consumption and small circuit area. However, CR-DAC is required 2 to the power of N unit capacitors to generate reference voltage for successive approximation of the N-bit SAR ADC, and many unit capacitors occupy large circuit area and consume more power. In order to improve this problem, this paper proposes SAR ADC using series capacitor DAC. The series capacitor DAC is required 2(1+N) unit capacitors to generate reference voltage for successive approximation and charges only two capacitors of the reference generation block. Because of these structural characteristics, the SAR ADC using series capacitor DAC can reduce the power consumption and circuit area. Proposed SAR ADC was designed in CMOS 180nm process, and at 1.8V supply voltage and 500kS/s sampling rate, proposed 6-bit SAR ADC have signal-to-noise and distortion ratio(SNDR) of 36.49dB, effective number of bits(ENOB) of 5.77-bit, power consumption of 294uW.

• International Journal of Control, Automation, and Systems
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• v.5 no.5
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• pp.501-507
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• 2007

This paper presents a new algorithm for the closed-loop $H_{\infty}$ control of a class of singularly perturbed nonlinear systems with an exogenous disturbance, using the successive Galerkin approximation (SGA). The singularly perturbed nonlinear system is decomposed into two subsystems of a slow-time scale and a fast-time scale in the spirit of the general theory of singular perturbation. Two $H_{\infty}$ control laws are obtained to each subsystem by using the SGA method. The composite control law that consists of two $H_{\infty}$ control laws of each subsystem is designed. One of the purposes of this paper is to design the closed-loop $H_{\infty}$ composite control law for the singularly perturbed nonlinear systems via the SGA method. The other is to reduce the computational complexity when the SGA method is applied to the high order systems.

• Structural Engineering and Mechanics
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• v.53 no.6
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• pp.1167-1182
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• 2015

In this study, the stresses and electric potential redistributions of a cylinder made from functionally graded piezoelectric material (FGPM) are investigated. All the mechanical, thermal and piezoelectric properties are modeled as power-law distribution of volume fraction. Using the coupled electro-thermo-mechanical relations, strain-displacement relations, Maxwell and equilibrium equations are obtained including the time dependent creep strains. Creep strains are time, temperature and stress dependent, the closed form solution cannot be found for this constitutive differential equation. A semi-analytical method in conjunction with the Mendelson method of successive approximation is therefore proposed for this analysis. Similar to the radial stress histories, electric potentials increase with time, because the latter is induced by the former during creep deformation of the cylinder, justifying industrial application of such a material as efficient actuators and sensors.