• ETRI Journal
• /
• v.28 no.4
• /
• pp.475-485
• /
• 2006

Network-on-chip (NoC) is an emerging design paradigm intended to cope with future systems-on-chips (SoCs) containing numerous built-in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC-based SoCs. Among the existing test issues for NoC-based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC-based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC-based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC'02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC-based SoCs.

• ETRI Journal
• /
• v.30 no.1
• /
• pp.129-140
• /
• 2008

In this paper, we propose a novel ant colony optimization (ACO)-based test scheduling method for testing network-on-chip (NoC)-based systems-on-chip (SoCs), on the assumption that the test platform, including specific methods and configurations such as test packet routing, generation, and absorption, is installed. The ACO metaheuristic model, inspired by the ant's foraging behavior, can autonomously find better results by exploring more solution space. The proposed method efficiently combines the rectangle packing method with ACO and improves the scheduling results by dynamically choosing the test-access-mechanism widths for cores and changing the testing orders. The power dissipation and variable test clock mode are also considered. Experimental results using ITC'02 benchmark circuits show that the proposed algorithm can efficiently reduce overall test time. Moreover, the computation time of the algorithm is less than a few seconds in most cases.

• Journal of Internet Computing and Services
• /
• v.6 no.2
• /
• pp.25-35
• /
• 2005

The Rate Monotonic(RM) scheduling algorithm and Earliest Deadline First(EDF) scheduling algorithm are normally used in Real-Time scheduling algorithm. In those scheduling algorithm, we could predict the performance possibility with total utilization value of task group. But. it had problems with prediction of the boundedness in individual task when the utilization value was over in temporary task. In this paper, the suggested scheduling algorithm can predict task when the utilization value was over and it suggested the method of predicting scheduling possibility based on the utilization value of individual task as well. it predicted the boundedness of scheduling possibility test through simulation In Real-Time scheduling algorithm and analyzed the result.

• Journal of Digital Contents Society
• /
• v.9 no.3
• /
• pp.471-481
• /
• 2008

Test scheduling considering power dissipation is an effective technique to reduce the testing time of complex SoCs and to enhance fault coverage under limitation of allowed maximum power dissipation. In this paper, a modeling technique of test resources and a test scheduling algorithm for efficient test procedures are proposed and confirmed. For test resources modeling, two methods are described. One is to use the maximum point and next maximum point of power dissipation in test resources, the other one is to model test resources by partitioning of them. A novel heuristic test scheduling algorithm, using the extended-tree-growing-graph for generation of maximum embedded cores usable simultaneously by using relations between test resources and cores and power-dissipation-changing-graph for power optimization, is presented and compared with conventional algorithms to verify its efficiency.

• Journal of Electrical Engineering and information Science
• /
• v.3 no.3
• /
• pp.396-401
• /
• 1998

An optimal algorithm is presented for feasibility test and scheduling of real-time tasks where tasks are preemptable and created dynamically. Each task has an arbitrary creation time, ready time, maximum execution time, and deadline. Feasibility test and scheduling are conducted via the same algorithm. Time complexity of the algorithm is O(n) for each newly created task where n is the number of tasks. This result improves the previous result of O(n log n). It is shown that the algorithm can be used for scheduling tasks with different levels of importance. Time complexity of the algorithm for the problem is O(n\ulcorner) which improves the previous results of O(n\ulcorner log n).

• Journal of Korean Society of Industrial and Systems Engineering
• /
• v.30 no.1
• /
• pp.59-65
• /
• 2007

HPI (High-speed Portable Internet) system which provides high speed internet services is going to be commercialized soon. Since HPI provides simultaneously four different service types such as UGS (Unsolicited Grant Service), rtPS (real time Polling Service), nrtPS(non-real time Polling Service), and BE (Best Effort) under different QoS (Quality of Service) requirements and limited wireless channel resources, efficient packet scheduling mechanisms are necessary to increase the utilization of channels as well as to satisfy the various QoS requirements. This study regards the traffic data to be served as time series and proposes a new packet scheduling algorithm based on the nonparametric statistical test. The performance of the newly proposed algorithm is evaluated through the simulation analysis using a simulator that can evaluate the performance of packet scheduling mechanisms under various values of system parameters and measures such as packet delay time, data transmission rate, number of loss packets, and channel utilization.

• Journal of Korean Institute of Industrial Engineers
• /
• v.35 no.1
• /
• pp.15-39
• /
• 2009

Advanced planning and scheduling (APS) refers to a manufacturing management process by which raw materials and production capacity are optimally allocated to meet demand. APS is especially well-suited to environments where simpler planning methods cannot adequately address complex trade-offs between competing priorities. However, most scheduling problems of APS in the real world face both inevitable constraints such as due date, capability, transportation cost, set up cost and available resources. In this survey paper, we address three crucial issues in APS, including basic scheduling model, job-shop scheduling (JSP), assembly line balancing (ALB) model, and integrated scheduling models for manufacturing and logistics. Several evolutionary algorithms which adapt to the problems are surveyed and proposed; some test instances based on the practical problems demonstrate the effectiveness and efficiency of evolutionary approaches.

• Journal of the Korea Safety Management & Science
• /
• v.25 no.2
• /
• pp.1-8
• /
• 2023

This paper is proposing a novel machine scheduling model for the unrelated parallel machine scheduling problem without setup times to minimize the total completion time, also known as "makespan". This problem is a NP-complete problem, and to date, most approaches for real-life situations are based on the operator's experience or simple heuristics. The new model based on the Memetic Algorithm, which was proposed by P. Moscato in 1989, is a hybrid algorithm that includes genetic algorithm and local search optimization. The new model is tested on randomly generated datasets, and is compared to optimal solution, and four scheduling models; three rule-based heuristic algorithms, and a genetic algorithm based scheduling model from literature; the test results show that the new model performed better than scheduling models from literature.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.3
• /
• pp.93-100
• /
• 2004

Test scheduling of SoC (System-on-a-chip) is very important because it is one of the prime methods to minimize the testing time under limited power consumption of SoC. In this paper, a heuristic algorithm, in which test resources are selected for groups and arranged based on the size of product of power dissipation and test time together with total power consumption in core-based SoC is proposed. We select test resource groups which has maximum power consumption but does not exceed the constrained power consumption and make the testing time slot of resources in the test resource group to be aligned at the initial position in test space to minimize the idling test time of test resources. The efficiency of proposed algorithm is confirmed by experiment using ITC02 benchmarks.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.1 s.343
• /
• pp.71-78
• /
• 2006

An NoC (Networks-on-Chip) is an emerging design paradigm intended to cope with a future SoC containing numerous built-in cores. In an NoC, the test strategy is very significant for its practicality and feasibility. Among existing test issues, TAM architecture and test scheduling will particularly dominate the overall test performance. In this paper, we address an efficient NoC test scheduling algorithm based on a rectangle packing approach used for an SoC test. In order to adopt the rectangle packing solution as an NoC test scheduling algorithm we design the configuration about test resources and test methods suitable for an NoC structure. Experimental results using some ITC'02 benchmark circuits show the proposed algorithm can reduce the overall test time by up to $55\%$ in comparison with previous works.