• Korean Journal of Materials Research
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• v.1 no.4
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• pp.191-197
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• 1991

The surface roughnesses of titanium silicide films and the diffusion behaviours of dopants in single crystal and polycrystalline silicon substrates durng titanium silicide formation by rapid thermal annealing(RTA) of sputter deposited Ti-filicide film from the composite $TiSi_{2.6}$ target were investigated by the secondary ion mass spectrometry(SIMS), a four-point probe, X-ray diffraction, and surface roughness measurements. The as-deposited films were amorphous but film prepared on single silicon substrate crystallized to the orthorhombic $TiSi_2$(C54 structure) upon rapid thermal annealing(RTA) at $800^{\circ}C$ for 20sec. There was no significant out-diffusion of dopants from both single crystal and polycrystalline silicon substrate into titanum silicide layers during annealing. Most of the implanted dopants piled up near the titanium silicide/silicon interface. The surface roughnesses of titanium silicide films were in the range between 16 and 22nm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.1-9
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• 2003

In this paper, a novel Ni silicide technology with Cobalt interlayer and Titanium Nitride(TiN) capping layer for sub 100 nm CMOS technologies is presented, and the device parameters are characterized. The thermal stability of hi silicide is improved a lot by applying co-interlayer at Ni/Si interface. TiN capping layer is also applied to prevent the abnormal oxidation of NiSi and to provide a smooth silicidc interface. The proposed NiSi structure showed almost same electrical properties such as little variation of sheet resistance, leakage current and drive current even after the post silicidation furnace annealing at $700^{\circ}C$ for 30 min. Therefore, it is confirmed that high thermal robust Ni silicide for the nano CMOS device is achieved by newly proposed Co/Ni/TiN structure.

• Korean Journal of Materials Research
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• v.31 no.2
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• pp.97-100
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• 2021

We report the effect of Standard Clean-1 (SC-1) cleaning to remove residual Ti layers after silicidation to prevent Al diffusion into Si wafer for Ti Schottky barrier diodes (Ti-SBD). Regardless of SC-1 cleaning, the presence of oxygen atoms is confirmed by Auger electron spectroscopy (AES) depth profile analysis between Al and Ti-silicide layers. Al atoms at the interface of Ti-silicide and Si wafer are detected, when the SC-1 cleaning is not conducted after rapid thermal annealing. On the other hand, Al atoms are not found at the interface of Ti-SBD after executing SC-1 cleaning. Al diffusion into the interface between Ti-silicide and Si wafer may be caused by thermal stress at the Ti-silicide layer. The difference of the thermal expansion coefficients of Ti and Ti-silicide gives rise to thermal stress at the interface during the Al layer deposition and sintering processes. Although a longer sintering time is conducted for Ti-SBD, the Al atoms do not diffuse into the surface of the Si wafer. Therefore, the removal of the Ti layer by the SC-1 cleaning can prevent Al diffusion for Ti-SBD.

• Analytical Science and Technology
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• v.5 no.2
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• pp.199-202
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• 1992

Ti-silicide was formed by using metal-Ti target and composite target on the silicon substrate that $BF_2$ were introduced into. Implant energies of $BF_2$ were 50keV and 90keV. The behavior of boron was investigated by SIMS. The redistribution of boron occurred during the formation of Ti-silicide by metal-Ti target and the sample implanted at the energy of 50keV showed severe out-diffusion. In the case that Ti-silicide was formed by composite target, there was little redistribution of boron.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.11
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• pp.1149-1155
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• 2004

In this paper, novel methods for improvement of thermal stability of Ni-germano Silicide were proposed for nano CMOS applications. It was shown that there happened agglomeration and abnormal oxidation in case of Ni-germano Silicide using Ni only structure. Therefore, 4 kinds of tri-layer structure, such as, Ti/Ni/TiN, Ni/Ti/TiN, Co/Ni/TiN and Ni/Co/TiN were proposed utilizing Co and Ti interlayer to improve thermal stability of Ni-germano Silicide. Ti/Ni/TiN structure showed the best improvement of thermal stability and suppression of abnormal oxidation although all kinds of structures showed improvement of sheet resistance. That is, Ti/Ni/TiN structure showed only 11 ohm/sq. in spite of 600 $^{\circ}C$, 30 min post silicidation annealing while Ni-only structure show 42 ohm/sq. Therefore, Ti/Ni/TiN structure is highly promising for nano-scale CMOS technology.

• Korean Journal of Materials Research
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• v.13 no.11
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• pp.711-716
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• 2003

Gate length, height, and silicide thickness have all been shrinking linearly as device density has progressively increased over the years. We investigated the effect of the cobalt diffusion during the silicide formation process on the 60$\AA$-thick gate oxide lying underneath the Ti/Co and Co/Ti bilayers. We prepared four different cobalt silicides, which have similar sheet resistance, made from the film structure of Co/Ti(interlayer), and Ti(capping layer)/Co, and peformed the current-voltage, time-to-break down, and capacitance-voltage measurements. Our result revealed that the cobalt silicide process without the Ti capping layer allowed cobalt atoms to diffuse into the upper interface of gate oxides. We propose that 100$\AA$-thick titanium interlayer may lessen the diffusion of cobalt to gate oxides in 1500-$\AA$ height polysilicon gates.

• Journal of the Korean institute of surface engineering
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• v.29 no.1
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• pp.3-14
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• 1996

High temperature anneal of W-rich silicides, inferior to adherence compared with Si-rich silicides, resulted in the film peeling off from the Si-substrate when WSix thickness reached more than critical thickness. Investigation of the W-rich silicide films peeling off from the substrate revealed that the voids underneath the $WSi_2$ produced through silicide reaction were responsible for the poor adherence of W-rich silicide. In addition, internal stress in the film increased as the silicide thickness increased. In order to promote the adhesion of WSix to Si-substrate, thin Ti-layer was formed between WSi and Si-substrate(WSix/Ti/Si). No voids were observed in $WSi_2$/Ti/Si $N_2$-annealed at $1000^{\circ}C$, thereby leading to an increase of the critical thickness from ～1700$\AA$ to more than 2500$\AA$. However, higher resisiti-vity was obtained in WSix/Ti/Si than in WSix/Si. Finally, different silicide reaction mechanism for the structures(WSix/Si, WSix/Ti/Si) was proposed to explain the formation of voids as well as the role of thin Ti-layer.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.61-61
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• 2000

Device의 고성능화를 위하여 소자의 고속화, 고집적화가 가속됨에 따라 SALICIDE Process가 더욱 절실하게 요구되고 있다. 이러한 SALICIDE Process의 재료로써는 metal/silicide 중에서 비저항이 가장 낮은 TiSi2(15-25$\mu$$\Omega$cm), CoSi2(17-25$\mu$$\Omega$cm)가 일반적으로 많이 연구되어 왔다. 그러나 Ti-silicide의 경우 Co-silicide는 배선 선폭의 감소에 따른 면저항 값의 변화가 작으며, 고온에서 안정하고, 도펀트 물질과 열역학적으로 안정하여 화합물을 형성하지 않는다는 장점이 있으마 Ti처럼 자연산화막을 제거할 수 없어 Si 기판위에 자연산화막이 존재시 균일한 실리사이드 박막을 형성할 수 없는 단점등을 가지고 있다. 본 연구에서는 Ti Capping layer 에 의한 균일한 Co-silicide의 형성을 일반적인 Si(100)기판과 SCl 방법에 의하여 chemical Oxide를 성장시킨 Si(100)기판의 경우에 대하여 연구하였다. 스퍼터링 방법에 의해 Co를 150 증착후 capping layer로써 TiN, Ti를 각각 100 씩 증착하였다. 열처리는 RTP를 이용하여 50$0^{\circ}C$~78$0^{\circ}C$까지 4$0^{\circ}C$ 구간으로 N2 분위기에서 30초 동안 열처리를 한후, selective metal strip XRD, TEM의 분석장비를 이용하여 관찰하였다. lst RTP후 selective metal strip 후 면저항의 측정과 XRD 분석결과 낮은 면저항을 갖는 CoSi2로의 상전이는 TiN capping과 Co 단일박막이 일반적인 Si(100)기판과 interfacial oxide가 존재하는 Si(100)기판위에서 Ti capping의 경우보다 낮은 온도에서 일어났다. 또한 CoSi에서 CoSi2으로 상전이는 일반적인 Si(100)기판위에서 보다 interfacial Oxide가 존재하는 Si(100)기판 위에 TiN capping과 Co 단일박막의 경우 열처리 후에도 Oxide가 존재하는 불균인한 CoSi2박막을 관찰하였으며, Ti capping의 경우 Oxise가 존재하지 않는 표면과 계면이 더 균일한 CoSi2 박막을 형성 할 수 있었다.

• Korean Journal of Materials Research
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• v.1 no.3
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• pp.168-174
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• 1991

Ti-silicide was deposited by sputtering the composite target($TiSi_{2.6}$) on single-Si wafers and oxide on them. The heat treatment temperatures by rapid thermal annealing(RTA) have been varied in the range of $600-850^{\circ}C$ for 20seconds. It was not until RTA temperature was $800^{\circ}C$ that a stable $TiSi_2$ was formed, and the value of resistivity of that phase was $27~29{\mu}{\Omega}-cm$, which seems a little higher than that formed by the reactive method. The result of x-ray diffraction peals showed that till $750^{\circ}C$, C49 $TiSi_2$ phase was dominant, but at $800^{\circ}C$, at last, the phase was transformed into a stable C54 $TiSi_2$ phase. And, the result of x-ray photoeletron spectroscopy(XPS) measurements showed that the composition ratio of Ti and Si was 2 1 in the case of specimens treated at $800^{\circ}C$, The surface roughness of $TiSi_2$, which was condidered a weak point, was improved to a superior value of $17{\pm}1nm$, therefore increasing the possibility of applying $TiSi_2$ to semiconductor devices.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.11
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• pp.887-893
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• 1991

To take advantage of Ti-polycide, when it is contacted with both n+ and p+ active area of silicon, the effects of BF$_2$ on the formation of Ti-silicide were investigated with RTA temperature and dopant concentration. The intermediate phase C49 TiSi$_2$ appeared at $650^{\circ}C$ and the stable phase C54 TiSi2 was formed at $700^{\circ}C$. And the formation of Ti-silicide was hindered by BF$_2$ doping and this trend was decreased with increasing temperature. The out-diffusion phenomena of BF$_2$ into Ti silicide were not observed. And significantly, the native oxide was a chief factor preventing the formation of Ti-silicides.