• The Transactions of the Korean Institute of Power Electronics
• /
• v.20 no.2
• /
• pp.167-174
• /
• 2015

This study describes how digital time delay deteriorates control performance in zero voltage switching (ZVS) phase-shifted full bridge (PSFB) converter. The small-signal model of the ZVS PSFB converter is derived from the buck-converter small-signal model. Digital time delay effects have been considered according to the digital sampling methods. The analysis verifies that digital time delays reduce the stability margin of the converter, and the double sampling technique exhibits better performance than the single sampling technique. Both simulation and experimental results based on 250 W ZVS PSFB confirm the validity of the analyses performed in the study.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.25 no.5
• /
• pp.677-684
• /
• 2021

This paper presents a time-to-digital converter for measuring absolute time differences. The time-to-digital converter was designed and fabricated in 0.18-um CMOS technology and it can be applied to Light Detection and Ranging system which requires long time-cover range and 50ps time resolution. Since designed time-to-digital converter adopted the reference clock of 625MHz generated by phase locked loop, it could have absolute time resolution of 50ps after automatic calibration and its cover range was over than 800ns. The time-to-digital converter adopted a counter and chain delay lines for time measurement. The counter is used for coarse time measurement and chain delay lines are used for fine time measurement. From many times experiments, fabricated time-to-digital converter has 50 ps time resolution with maximum INL of 0.8 LSB and its power consumption is about 70 mW.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.5
• /
• pp.323-328
• /
• 2001

A new time-to-digital converter is proposed which is based on a capacitor and a counter. The conventional time-to-digital converter requires rather longer processing time than the input time interval to obtain an accurate digital output. The resolution of the converted digital output is constant independent on the input time interval. However this study proposes the circuit in which the converted digital output can be obtained without delay time, and both the input time interval and the resolution can be easily improved through controlling passive device parameters.

• Journal of Electrical Engineering and Technology
• /
• v.9 no.5
• /
• pp.1551-1561
• /
• 2014

Design, Simulation and experimental analysis of closed loop time domain based Discrete PWM buck-boost converter are described. To improve the transient response and dynamic stability of the proposed converter, Discrete PID controller is the most preferable one. Discrete controller does not require any precise analytical model of the system to be controlled. The control system of the converter is designed using digital PWM technique. The proposed controller improves the dynamic performance of the buck-boost converter by achieving a robust output voltage against load disturbances, input voltage variations and changes in circuit components. The converter is designed through simulation using MATLAB/Simulink and performance parameters are also measured. The discrete controller is implemented, and design goal is achieved and the same is verified against theoretical calculation using LabVIEW.

• Journal of information and communication convergence engineering
• /
• v.8 no.1
• /
• pp.103-106
• /
• 2010

In this paper, the delay times were evaluated to develop highly reliable time-to-digital converter(TDC) in analog and digital delay element structures. The delay element can be designed by using current source or inverter. In case of using inverter, the number of inverter has to be controlled to adjust the delay time. And in case of using current source, the current for charging and discharging is controlled. When the current source is used the delay time of the delay element is not sensitive with varying the channel width of CMOS. However, when the inverter is used the delay time is directly related to the channel width of CMOS. Therefore to obtain good reliability in TDC circuit the delay element using current source is more stable compared to inverter in the viewpoint of the variation of fabrication process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2017.10a
• /
• pp.522-523
• /
• 2017

Analog-to-Digital converter is designed using a current conveyor circuit and a time-to-digital converter. The analog voltage is sampled using the current conveyor circuit and then the voltage is converted to time information by the discharge of the sampling voltage. The time information is converted to digital value by the counter-type time-to-digital converter. In order to reduce the converted error the clock is synchronized with the time information pulse.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.2
• /
• pp.7-13
• /
• 2011

This paper presents a Time-to-Digital Converter which is a key block of an All-Digital Phase Locked Loop. In this work, a Vernier Delay Line is added in a conventional Gated Ring Oscillator, so it could get multi-phases and a high resolution. The Gated Ring Oscillator uses 7 unit delay cell, the Vernier Delay Line is used each delay cell. So proposed Time-to-Digital Converter uses total 21 phases. This Time-to-Digital Converter circuit is designed and laid out in $0.13{\mu}m$ 1P-6M CMOS technology. The proposed Time-to-Digital Converter achieves 26ps resolution, maximum input signal frequency is 100MHz and the digital output of proposed Time-to-Digital Converter are 8-bits. The proposed TDC detect 5ns phase difference between Start and Stop signal. A power consumption is 8.4~12.7mW depending on Enable signal width.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.12 no.4
• /
• pp.411-417
• /
• 2012

A Coarse-Fine Time-to-Digital Converter (TDC) using the single time amplifier is proposed. A vernier delay line is used to overcome process dependency and the 2-stage time amplifier is designed to have high resolution by increasing the gain of the time amplifier. Single time amplifier architecture reduces the silicon area of the TDC and alleviates mismatch effect between time amplifiers. The proposed TDC is implemented in $0.18{\mu}m$ CMOS process with the supply voltage of 1.8 V. The measured results show that the resolution of the TDC is 0.73 ps with 10-bit digital output, although highend process is not applied. The single time amplifier architecture reduces 13% of chip area compared to previous work. By reducing the supply voltage, the linearity of the TDC is enhanced and the resolution is decreased to 1.45 ps.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.23 no.7
• /
• pp.816-821
• /
• 2019

A counter-type time-to-digital converter was designed using a dual edge T flip-flop. The time-to-digital converter was designed with a $0.18{\mu}m$ CMOS process at a supply voltage of 1.5 volts. In a typical time-to-digital converter, when the period of the clock is T, a conversion error corresponding to the period of the clock occurs due to the asynchronism between the input signal and the clock. However, the clock of the time-to-digital converter proposed in this paper is generated in synchronization with the start signal which is the input signal. As a result, conversion errors that may occur due to asynchronization of the start signal and the clock do not occur. The flip-flops constituting the counters are composed of dual-edge flip-flops operating at the positive and negative edges of the clock to improve the resolution.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.2
• /
• pp.145-151
• /
• 2013

In this paper, a low power, small area cyclic time-to-digital converter in All-Digital PLL for DVB-S2 application is presented. Coarse and fine TDC stages in the two-step TDC are shared to reduce the area and the current consumption maintaining the resolution since the area of the TDC is dominant in the ADPLL. It is implemented in a 0.13 ${\mu}m$ CMOS process with a die area of 0.12 $mm^2$. The power consumption is 2.4 mW at a 1.2 V supply voltage. Furthermore, the resolution and input frequency of the TDC are 5 ps and 25 MHz, respectively.