• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.124-131
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• 2014

This paper describes a design of an adaptive baseband modem based on TDMA(time division multiple access) with a relay protocol function for wireless personal area networks. The designed baseband modem is controlled by a master synchronization signal and can be configured a relay network up to 14 hops. For efficient data relay communications, the internal buffer design is optimized by implementing a priority memory bus controller to a single port memory. And the priority memory bus controller is also designed to minimize the number of synthesized logic gates. To implement the synchronization function of the narrowband TDMA relay communication, the number of gates has been reduced by dividing the frame synchronization circuits and the network slot synchronization circuits. By using these methods, the number of gates are used about 37%(34,000 gates) on Xilinx FPGA XC6SLX9 which has 90,000 gates. For the 1024-bit frame size with a 32-bit synchronization word, the communication reception rate is 96.4%. The measured maximum transmission delay of the designed baseband modem is 230.4 msec for the 14-hop relay communication.

• 전기의세계
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• v.28 no.1
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• pp.43-52
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• 1979

Recently, interest in multivalued(MV) logic system has been increased, despites the apparent difficulties for practical application. This is because of the many advantages of the MV compared with the 2-valued logic systems, such as; (a) higher speed of arithmetical operation on account of the smaller number of digits required for a given data, (b) better utilization of data transmission channels on account of the higher information contents per line, (c) potentially higher density of information storage. This paper describes a MV switching theory and experimental MV logic elements based on current-mode logic technique. These elements tried were a 3-stable pulse generator, a ternary AND, a ternary OR, a MT circuit and a ternary inverter. Tristable flops which are indispensable for constituting a ternary shift register are synthesized using these gates. A BCD to TCD decoder, and vice versa, are proposed by using a ternary inverter and some binary gates. Thus, the feasibility of a large scale MV digital system has been demonstrate.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.3
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• pp.488-493
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• 2008

This paper represents a dual-mode type transmission technique for a high reliable narrow-band power line communication(PLC) modem, and its design and implementation of a system-on-chip(SoC). The proposed transmission technique is based on a Chirp modulation for the purpose of overcoming time variations of power line channel environments in the narrow-bandwidth of the frequency range of 95-145.5 kHz. The designed modem is fabricated utilizing a mixed 0.18 ${\mu}m$ CMOS technology. Especially, according to the power line channel environments the data transmission rate can be selectively changed into 2.5 kbps and 480 bps. The total hardware complexity of the implemented chip is about 50,000 gates, the power consumption is about 26mW, and the operating frequency is up to 5.12 MHz.

• International Journal of Control, Automation, and Systems
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• v.2 no.1
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• pp.23-38
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• 2004

We proposed the infinity control principle to evaluate the Biological function. The H infinity control was applied to the Sodium (Na) ion selective gating channel on the excitable cellular membrane of the neural system. The channel opening, closing and inactivation processes were expressed by movements of three gates and one inactivation blocking particle in the channel pore. The rate constants of the channel state transition were set to be voltage dependent. The temporal changes in amounts per unit membrane area of the channel states were expressed by means of eight differential equations. The biochemical mimetic used to complete the Na ion selective channel was regarded as noise. The control inputs for ejecting the blocking particle with plugging in the channel pore were set for the active transition from inactivated states to a closed or open state. By applying the H infinity control, we computed temporal changes in the channel states, observers, control inputs and the worst case noises. The present paper will be available for evaluating the noise filtering function of the biological signal transmission system.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.47-50
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• 2004

In this paper, we implement an Elliptic Curve Cryptosystem(ECC) processor for DTCP. Because DTCP(Digital Transmission Content Protection) uses GF(p), where p is a 160-bit prime integer, we design a scalar multiplier based on GF(p). The scalar multiplier consists of a modular multiplier and an adder. The multiplier uses montgomery algorithm which is implemented with CSA(Carry-save Adder) and CLA(Carry-lookahead Adder). Our new scalar multiplier has been synthesized using Samsung 0.18 um CMOS technology and the maximum operation frequency is estimated 98 MHz, with the size about 65,000 gates. The resulting performance is 29.6 kbps, that is, it takes 5.4 msec to process a 160-bit data frame. We assure that this performance is enough to be used for digital signature, encryption/decryption, and key exchanges in real time environments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.8 no.4
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• pp.156-163
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• 1983

A composite DPCM system is designed and implemented for the transmission of a NTSC color TV signal over a 44, 736Mbps channel. It is based on an intra-field fourth-order linear predictor and a nonlinear quantizer of five bits. The predictor preserves both the luminance and the chrominance components through one predictor. To accomodate the speed requirement for real time processing, mainly high speed ECL gates and memory devices are used in the hardware implementation. Experimental results show that this composite DPCM system can be applicable for a practical transmission of color TV signal with CATV quality.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.281-284
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• 2003

Multi-code CDMA is an appropriate scheme for transmitting high rate data. However, dynamic range of the signal is large, and power amplifier with good linearity is required. Code select CDMA (CS/CDMA) is a variation of multi-code CDMA scheme that ensures constant amplitude transmission. In CS/CDMA input data selects multiple orthogonal codes, and sum of these selected codes are MPSK modulated to convert multi-level symbol into different carrier phases. CS/CDMA system employs level clipping to limit the number of levels at the output symbol to avoid hish density of signal constellation. In our previous work we showed that by encoding input data of CS/CDMA amplitude of the output symbol can be made constant. With this coding scheme, level clipping is not necessary and the output signal can be BPSK modulated for transmission. In this paper we show that the constant amplitude coded(CA-) CS/CDMA transmitter can be implemented using only logic gates, and the hardware complexity is very low. In the proposed transmitter architecture there is no apparent redundant encoder block which plays a major role in the constant amplitude coded CS/CDMA.

• Journal of IKEEE
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• v.21 no.3
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• pp.256-259
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• 2017

SENT (single edge nibble transmission) is a serial communication protocol between automotive sensors and ECU (electronic control unit). SENT exploits digital waveform, so it has a simple and cheap architecture without transceiver circuits. Usually it is exploited as an embedded communication interface in the sensors. In this paper, a SENT interface was designed in Verilog HDL, fully complying with SAE J2716. It was implemented in FPGA, and verified on a test board. When it was synthesized, the gate count is about 2,500 gates in 0.18um technology.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.5
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• pp.108-116
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• 1989

The simulator described here-LOSIM(LOgic SIMulator)-was developed to verify the logic design for VLSI(Very Large Scale Integrated) circuits at mixed level. In this paper, we present a modeling approach to obtain more accurate results than conventional logic simulators [5-6,9] for general elements, functional elements, transmission gates and tri-state gates using eight signal values and two gignal strengths. LOSIM has the capability which can perform timing and hazard analysis by using assignable rise and fall delays. We also prosent an efficient algorithm to accurately detectdynamic and static hazards which may be caused by the circuit delays. Our approach is based on five logic values and the scheduled time. LOSIM has been implemented on a UN-3/160 workstation running Berkeley 4.2 UNIX, and the program is written in C language. Static RAM cell and asynchronous circuit are illustrated as an example.

• Journal of Photoscience
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• v.9 no.2
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• pp.317-319
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• 2002

All-optical switching has been demonstrated in bacteriorhodopsin (bR) based on nonlinear intensity induced excited state absorption. The transmission of a cw probe laser beam at 410 nm corresponding to the peak absorption of M state through a bR film is switched by a pulsed pump laser beam at 570 nm that corresponds to the maximum initial 8 state absorption. The switching characteristics have been analyzed using the rate equation approach considering all the six intermediate states (B, K, L, M, N and 0) in the bR photocycle. The switching characteristics are shown to be sensitive to life time of the M state, absorption cross-section of the 8 state at probe wavelength ($\sigma$ $\_$Bp/) and peak pump intensity. It has been shown that the probe laser beam can be completely switched off (100 % modulation) by the pump laser beam at relatively low pump powers, for $\sigma$$\_$Bp/ = O. The switching characteristics have been used to design all-optical NOT, OR, AND and the universal NOR and NAND logic gates for optical computing with two pulsed pump laser beams.