• Title/Summary/Keyword: VDL and so on

Search Result 3, Processing Time 0.016 seconds

The study for Installation an intelligent AtoN AIS (지능형 해양교통 안전망 구축을 위한 조사)

  • Choi, Yeong-Jong
    • Proceedings of the Korean Institute of Navigation and Port Research Conference
    • /
    • 2009.06a
    • /
    • pp.535-537
    • /
    • 2009
  • For decreasing the maritime pollution accident of the large material(crude oil, ore and so on) carrier, as we construct the Virtual AtoN AIS utilizing the existing AIS Base Station in the area of major route, passage way and danger or in case of emergency danger, it can help the normal vessel to pass the area without any obstacles and inform the danger elements to AIS. ECDIS and radar of the large carrier.

  • PDF

A Study on Real-time Message Analysis for AIS VDL Load Management (AIS 통신부하 관리를 위한 실시간 메시지 분석에 관한 연구)

  • Lee, Sang-Jae;Jeong, Jung-Sik;Kim, Min-Yeop;Park, Gyei-Kark
    • Journal of the Korean Institute of Intelligent Systems
    • /
    • v.23 no.3
    • /
    • pp.256-261
    • /
    • 2013
  • The AIS(Automatic Identification System) has been widely used for ship safety at sea over the last 10 years. The AIS traffic load at VDL(VHF Data Link) has been continuously increased. As the traffic load at VDL increases, the quality of AIS service may be deteriorated. In the previous research, the AIS traffic has been analyzed in the major ports of Korea, and its problem due to traffic overload has been suggested. However, no solutions has been given so far. In this paper, the method of autimatically controlling the VDL traffic at AIS base station is represented.

Design of a 26ps, 8bit Gated-Ring Oscillator Time-to-Digital Converter using Vernier Delay Line (버니어 지연단을 이용한 26ps, 8비트 게이티드 링 오실레이터 시간-디지털 변환기의 설계)

  • Jin, Hyun-Bae;Park, Hyung-Min;Kim, Tae-Ho;Kang, Jin-Ku
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.48 no.2
    • /
    • pp.7-13
    • /
    • 2011
  • This paper presents a Time-to-Digital Converter which is a key block of an All-Digital Phase Locked Loop. In this work, a Vernier Delay Line is added in a conventional Gated Ring Oscillator, so it could get multi-phases and a high resolution. The Gated Ring Oscillator uses 7 unit delay cell, the Vernier Delay Line is used each delay cell. So proposed Time-to-Digital Converter uses total 21 phases. This Time-to-Digital Converter circuit is designed and laid out in $0.13{\mu}m$ 1P-6M CMOS technology. The proposed Time-to-Digital Converter achieves 26ps resolution, maximum input signal frequency is 100MHz and the digital output of proposed Time-to-Digital Converter are 8-bits. The proposed TDC detect 5ns phase difference between Start and Stop signal. A power consumption is 8.4~12.7mW depending on Enable signal width.