• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.369-372
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• 2001

This paper presents the design of high-speed virtual output queue(VOQ) management scheme for high performance cell/packet switch, which has a serial cross bar structure. The proposed VOQ management scheme has been designed for wire-speed routing with a pipelined buffer management. It provides the tolerance of requests and grants data transmission latency between the VOQ manager and central arbiter using a new request control method that is based on a high-speed shifter. The designed VOQ manager has been implemented in a field programmable gate array chip with a 77MHz operating frequency, a 900-pin fine ball grid array package, and 16$\times$16 switch size.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10c
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• pp.201-203
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• 2000

VOQ 방법은 입력 큐잉의 저 비용과 출력 큐잉의 고성능이라는 장점을 결합한 효과적인 큐잉방법이다. VOQ를 효과적으로 사용하기 위해서는 셀의 순서를 스케쥴 해주는 스케쥴링 알고리즘이 필요하다. 본 논문에서는 기존의 iSlip, RRM의 round-robin based priority 방식을 따르면서 큐의 현재 상태에 따라서 스케쥴링을 달리하는 알고리즘을 제시하였다. 이 알고리즘에서는 큐에 대한 threshold값을 설정하고 큐에 저장하고 있는 셀의 수가 threshold값 보다 클 경우 그 큐의 셀을 연속해서 포워딩 하도록 하였다. 시뮬레이션을 통해 본 논문에서 제시한 알고리즘과 기존의 iSlip 알고리즘과의 성능을 패킷의 지연시간 측면에서 비교해 보았다.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.347-350
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• 2002

In the input buffer switch system, VOQ(Virtual Output Queue) archives 100% throughput. The VOQ with the systolic architecture maintains an uniform performance regardless of a number of Packet class and output port, so that it doesn't have a limitation of scalability. In spite of these advantages, the systolic architecture VOQ is difficult to change sorting order In this paper, we Proposed a systolic architecture VOQ which support weighted round robin(WRR) algorithm to provide with flow control service.

• Proceedings of the Korean Information Science Society Conference
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• 2001.04a
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• pp.415-417
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• 2001

RED 알고리즘은 큐 avg가 threshold를 넘으면 일정한 확률로 패킷을 drop하여 congestion을 제어하는 알고리즘이다. RED 알고리즘은 큐 자신의 avg만을 고려하여 drop 확률을 결정한다. 하지만, VOQ를 사용하는 input queueing에서 같은 출력 단을 목적지로 하는 다른 큐들의 사이즈가 큐 내부에서의 delay에 영향을 미치기 때문에 그 큐들의 avg를 고려하는 것이 필요하다. 본 논문에서는 기존의 RED 방법의 drop 확률 결정에서 같은 출력 단을 목적지로 하는 큐들의 avg 값을 고려하는 알고리즘을 제안한다. 시뮬레이션을 통하여 제안한 알고리즘을 구현하고, 성능을 기존의 RED 알고리즘과 비교한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.133-142
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• 2004

Recently, the growth of Internet and a variety of multimedia services through Internet increasingly demands high-speed packet transmission, the new routing function, and QoS guarantee on conventional routers. Thus, a new switching mechanical called the MPLS(Multi-Protocol Label Switching), was proposed by IETF(Internet Engineering Task Force) as a solution to meet these demands. In addition the deployment of MPLS network supporting Differentiated Services is required. In this paper, we propose the architecture of the MPLS switch supporting Differentiated Services in the MPLS-based network. The traffic conditioner consists of a classifier, a meter, and a marker. The VOQ-PHB module, which combines input Queue with each PHB queue, is implemented to utilize the resources efficiently. It employs the Priority-iSLIP scheduling algorithm to support high-speed switching. We have designed and verified the new and fast hardware architecture of VOQ-PHB and the traffic conditioner for QoS and high-speed switching using NS-2 simulator. In addition, the proposed architecture is modeled in VHDL, synthesized and verified by the VSS analyzer from SYNOPSYS. Finally, to justify the validity of the hardware architecture, the proposed architecture is placed and routed using Apollo tool.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.11b
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• pp.1217-1220
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• 2002

인터넷 트랙픽의 급격한 증가에 따라, 새로운 멀티미디어 서비스의 요구를 수용하기 위해서 MPLS가 제안되었으며, MPLS는 QoS를 보장하는 Differentiated Service클 제공하는 방향으로 진화되고 있다. 또한 MPLS에서 Giga/Tera 라우터에서 제공하는 고속의 스위칭과 확장성을 보장할 필요성이 증가되었다. 본 논문에서는 고속의 스위칭이 가능하고 QoS를 보장하는 MPLS 라우터의 구조를 제안한다. 스위치는 입력 큐잉 방식으로 QoS를 보장하도록 VOQ와 PHB별 큐를 확장한 방식이며, 이의 스케쥴링 알고리즘으로는 Priority-iSLIP 알고리즘을 사용하였다. 제안한 구조는 NS-2 시뮬레이터로 모델링하여 검증하였다.

• The Journal of the Korea Contents Association
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• v.5 no.3
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• pp.217-225
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• 2005

Currently the research on input-queued ATM switches is one of the most active research fields. Many achievements have been made in the research on scheduling algorithms for input-queued ATM switches and also applied in commerce. The scheduling algorithms have the characteristics of improving throughput, satisfying QoS requirements and providing service fairly. In this paper, we studied on an implementation of scheduler which arbitrates the input-queued ATM switches efficiently and swiftly. The proposed scheduler approximately provides $100\%$ throughput for scheduling. The proposed algorithm completes the arbitration for N-port VOQ switch with 4-iterative matching. Also the proposed algorithm has a merit for implementing the scheduling algorithm with 1/2 area compared to that of iSLIP scheduling algorithm which is widely used. The performance of the proposed scheduling algorithm is superior to that of iSLIP in 4-iterative matching.

• Journal of Internet Computing and Services
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• v.8 no.5
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• pp.161-170
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• 2007

The proposed switch which has separated data plane and switching plane can make parallel processing for packet data storing, memory address pointer switching and simultaneously can be capable of switching the variable length for IP packets. The proposed architecture does not require the complicated arbitration algorithms in VOQ, also is designed for QoS of generic output queue switch as well as input queue. At the result of simulations, the proposed architecture has less average packet delay than the one of the memory-sharing based architecture and guarantees keeping a certain average packet delay in increasing switch size.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.4
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• pp.629-637
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• 2006

Currently the research on input-queued ATM switches is one of the most active research fields. Many achievements have been made in the research on scheduling algorithms for input-queued ATM switches and also applied in commerce. The scheduling algorithms have the characteristics of improving throughput, satisfying QoS requirements and providing service fairly. In this paper, we studied on an implementation of scheduler which arbirates the input-queued ATM switches efficiently and swiftly. The proposed scheduler approximately provides 100% throughput for scheduling. The proposed algorithm completes the arbitration for N-port VOQ switch with 4-iterative matching. Also the proposed algorithm has a merit for implementing the scheduling algorithm with 1/2 area compared to that of iSLIP scheduling algorithm which is widely used. The performance of the proposed scheduling algorithm is superior to that of iSLIP in 4-iterative matching. The proposed scheduling algorithm was implemented in FPGA and verified on board-level.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1A
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• pp.114-121
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• 2000

The problem of an input-buffered switch is the HOL(head-of-line) blocking which limits the maximum throughput but it is easy to implement in hardware. However, HOL blocking can be eliminated using aVOQ(virtual-output-queueing) technique. 0 this paper, we propose a new cell-scheduling algorithm for aninput-buffered ATM switch. The proposed algorithm, called PPIM(Probabilistic Parallel Iterative Matching), imposesa weight to every request based on the reserved bandwidth. It is shown that the input-buffered ATM switch withthe proposed PPIM algorithm not only provides high throughput and low delay but it also reduces the jitter,compared with the existing WPIM(Weighted PIM).