• Journal of Institute of Control, Robotics and Systems
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• v.14 no.8
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• pp.824-836
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• 2008

Relaxed static stability(RSS) concept has been applied to improve aerodynamic performance of modern version supersonic jet fighter aircraft. Therefore, flight control systems are necessary to stabilize an unstable aircraft, and provides adequate handling qualities and achieve performance enhancements. Standard FCSDVP (Flight Control System Design and Verification Process) is provided to reduce development period of the flight control system. In addition, if this process is employed in developing flight control system, it reduces the trial and error for development and verification of flight control system. This paper addresses the flight control system design and verification process for the RSS aircraft utilizing design goal based on military specifications, linear and nonlinear system design and verification based on universal software, handling quality test based on HILS(Hardware In-the-Loop Simulator) environment, and ground and flight test results to verify aircraft dynamic flight responses.

• Proceedings of the KSR Conference
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• 2009.05a
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• pp.483-494
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• 2009

Since the embedded system is more intelligent, the importance of the reliability in the embedded system is a lot more visible. Especially the reliability of the embedded system in the train control system is even better important. As the special quality of the embedded system, the hardware of the system is directly controlled by the software in the embedded system. As the expansion of complexity, the expense amd the time for verification is required more and more. This paper is presented the verification of the reliability as the method with background of failure Embedded system is gradually, the importance of 'A built-in on the system embedded system's reliability is focused. In particular, in the train control system built-in of the embedded system, reliability is even more important. The embedded system of the system controls over hardware, software with built-in directly. The more complex system is, the more increasable of depending on the reliability of the time verification and expensive is. This paper is about he characteristics of the reliability and verification of embedded system under the failure mechanisms, based on the verification methodology suggested by in the train control system.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.30 no.7 s.250
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• pp.816-825
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• 2006

This paper describes the development of a web-based interference verification system in the mold design process. Although several commercial CAD systems furnish interference verification functions, those systems are very expensive and inadequate to perform collaborative works over the Internet. In this paper, an efficient and precision hybrid interference verification algorithm for the web-based interference verification system over the distributed environment has been studied. The proposed system uses lightweight CAD files produced from the optimally transformed CAD data through ACIS kernel and InterOp. Collaborators related to the development of a new product are able to verify the interference verification over the Internet without commercial CAD systems. The system reduces production cost, errors and lead-time to the market. Validity of the developed system is confirmed through case studies.

• THE INTERNATIONAL COMMERCE & LAW REVIEW
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• v.58
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• pp.267-286
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• 2013

Origin verification is regarded most essential for FTA performance administration. This administration is divided into direct and indirect system where Korea has adapted indirect system to Korea-EU FTA while direct system to Korea-USA FTA. A comparative analysis was conducted on the system of origin verification and provisions contained in preferential tariff law of each countries. The study finds that Korean origin verification system is a bit lack of procedural provision resulting in less protection of domestic trader's rights. Another point is that Korean Customs Authority is weak, in respect of organization and man power, to protect illegal bilateral tariff application by counter part FTA countries. And therefore this study suggests the policy makers to arrange detailed FTA origin verification procedures with earliest meeting with counter part FTA countries, and further stress that make up of organization and man power for origin verification in a timely manner.

• Journal of the Semiconductor & Display Technology
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• v.23 no.1
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• pp.25-35
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• 2024

In the present modern day, as the complexity and size of SoC(System on Chip) increase, the importance of design verification are increasing, Therefore it takes a lot of time to verify the design. There is an emerging need to manage the verification environment faster and more efficiently by reusing the existing verification environment. UVM-based verification is a standardized and highly reliable verification method widely adopted and used in the semiconductor industry. This paper presents a UVM-based verification for the 4 tap equalizer module with a systolic array structure. Through the constraints randomization, it was confirmed that various test scenarios stimulus were generated. In addition, by verifying a simulation comparing the actual DUT outputs with the MATLAB reference outputs, the reuse and efficiency of the UVM test bench could be confirmed.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.274-279
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• 2009

The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In this paper, verification environments based-on SystemVerilog and SystemC, one is native-code co-verification environment which makes prompt functional verification possible and another is SystemVerilog layered testbench which makes clock-level verification possible, are implemented. In native-code co-verification, HW and SW parts of SoC are respectively designed with SystemVerilog and SystemC after HW/SW partitioning using SystemC, then the functional interaction between HW and SW parts is carried out as one simulation process. SystemVerilog layered testbench is a verification environment including corner case test of DUT through the randomly generated test-vector. We adopt SystemC to design a component of verification environment which has multiple inheritance, and we combine SystemC design unit with the SystemVerilog layered testbench using SystemVerilog DPI and ModelSim macro. As multiple inheritance is useful for creating class types that combine the properties of two or more class types, the design of verification environment adopting SystemC in this paper can increase the code reusability.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2003.09a
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• pp.216-219
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• 2003

Among the techniques to protect private information by adopting biometrics, speaker verification is expected to be widely used due to advantages in convenient usage and inexpensive implementation cost Speaker verification should achieve a high degree of the reliability in the verification nout the flexibility in speech text usage, and the efficiency in verification system complexity. Continuants have excellent speaker-discriminant power and the modest number of phonemes in the category, and multilayer perceptrons (MLPs) have superior recognition ability and fast operation speed. In consequence, the two provide viable ways for speaker verification system to obtain the above properties. This paper implements a system to which continuants and MLPs are applied, and evaluates the system using a Korean speech database. The results of the experiment prove that continuants and MLPs enable the system to acquire the three properties.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.2
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• pp.145-149
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• 2011

Recently, as the design of a system gets larger and more complex, functional verification method based on system-level becomes more important. The verification of a functional block mainly uses BFM(bus functional model). The larger the burden on functional verification is, the more the importance of configuring a proper verification environment increases rapidly. SystemVerilog unifies hardware design languages and verification languages in the form of extensions to the Veri log HDL. The processing of design description, function simulation and verification using same language has many advantages in system development. In this paper, we design DUT that is composed of AMBA bus and function blocks using SystemVerilog and verify the function of DUT in verification environment using layered testbench. Adaptive FIR filter and Booth's multiplier are chosen as function blocks. We confirm that verification environment can be reused through a minor adaptation of interface to verify functions of other DUT.

• Proceedings of the KSR Conference
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• 2010.06a
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• pp.1821-1828
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• 2010

In this study we suggest a method of optimization of verification hierarchy structure and system requirements management by using a verification matrix with traceability consideration. Verification items were gathered in the process of CDR(Critical Design Review), and analyzed with respect to requirements traceability structure. Missed or overlapped items were adjusted, and cross-correlated items between sub-systems were clustered and rearranged in order to structurize verification requrements (VRs). Those VRs are to be used as a guideline for the test and evaluation planning, development of test items and procedure, and system requirements management throughout the system integration stages.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.3C
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• pp.257-267
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• 2009

This paper presents a training method for neural networks and the employment of MSE (mean scare error) values as the basis of a decision regarding the identity claim of a speaker in a recurrent neural networks based speaker verification system. Recurrent neural networks (RNNs) are employed to capture temporally dynamic characteristics of speech signal. In the process of supervised learning for RNNs, target outputs are automatically generated and the generated target outputs are made to represent the temporal variation of input speech sounds. To increase the capability of discriminating between the true speaker and an impostor, a discriminative training method for RNNs is presented. This paper shows the use and the effectiveness of the MSE value, which is obtained from the Euclidean distance between the target outputs and the outputs of networks for test speech sounds of a speaker, as the basis of speaker verification. In terms of equal error rates, results of experiments, which have been performed using the Korean speech database, show that the proposed speaker verification system exhibits better performance than a conventional hidden Markov model based speaker verification system.