• Journal of electromagnetic engineering and science
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• v.18 no.1
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• pp.35-40
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• 2018

This study presents a vertical-type CMOS Hall device with improved sensitivity to detect a 3D magnetic field in various types of sensors or communication devices. To improve sensitivity, trenches are implanted next to the current input terminal, so that the Hall current becomes maximum. The effect of the dimension and location of trenches on sensitivity is simulated in the COMSOL simulator. A vertical-type Hall device with a width of $16{\mu}m$ and a height of $2{\mu}m$ is optimized for maximum sensitivity. The simulation result shows that it has a 23% better result than a conventional vertical-type CMOS Hall device without a trench.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.10
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• pp.1890-1896
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• 2008

In this paper, the Si vertical Hall devices ale fabricated by using standard bipolar process and investigated in terms of the opeating and noise properties. The sensitivity of device with P+ isolation dam(type B) has been increased up to about 1.2 times compared to that device without the dam also noise has been increased. With the condition of f=I[KHz], band-width 1[Hz], the resolution of magnetic-field detection were about $0.97[{\mu}T]$/ type B and $1.25[{\mu}T]$/ type A, respectively, thus we must consider correlation the low noise or good resolution and high sensitivity in the situation for device geometry design or even for the materials.

• Journal of Sensor Science and Technology
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• v.23 no.6
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• pp.392-396
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• 2014

The 2-dimensional silicon vertical Hall devices, which are sensitive to X,Y components of the magnetic field parallel to the surface of the chip, are fabricated using a modified bipolar process. It consists of the thin p-layer at Si-$SiO_2$ interface and n-epi layer to improve the sensitivity and influence of interface effect. Experimental samples are a sensor type K with and type J without $p^+$ isolation dam adjacent to the center current electrode. The results for both type show a more high sensitivity than the former's 2-dimensional vertical Hall devices and a good linearity. The measured non-linearity is about 0.8%. The sensitivity of type J and type K are about 66 V/AT and 200 V/AT, respectively. This sensor's behavior can be explained by the similar J-FET model.

• Journal of Sensor Science and Technology
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• v.20 no.4
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• pp.260-265
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• 2011

The silicon vertical hall devices are fabricated using a modified bipolar process. It consists of the thin p-layer at Si-$SiO_2$, interface and n-epi layer without $n^+$buried layer to improve the sensitivity and influence of interface effects. Experimental samples are a sensor type I with and type H without p+isolation dam adjacent to the center current electrode. The experimental results for both type show a more high current-related sensitivity than the former's vertical hall devices. The sensitivity of type H and type I are about 150 V/AT and 340 V/AT, respectively. This sensor's behavior can be explained by the similar J-FET model.