• 제목/요약/키워드: WAFER

검색결과 3,158건 처리시간 0.032초

클린튜브 시스템의 웨이퍼 운동 제어 (Wafer Motion Control of Clean Tube System)

  • 신동헌;최철환;정규식
    • 설비공학논문집
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    • 제16권5호
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    • pp.475-481
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    • 2004
  • This paper presents a force model of the clean tube system, which was developed as a means of transferring air-floated wafers inside a closed tube filled with super clean air. The recovering force from the holes for floating wafers is modeled as a linear spring and thus the wafers motion is modeled as a mass-spring-damper system. The propelling forces are modeled as linear along with the wafer location. The paper also proposes a control method to emit and stop a wafer at the center of a control unit. It reveals the minimum value of the propelling force to leave from the control unit. In order to stop the wafer, it utilizes the exact time when the wafer arrives at the position to activate the propelling force. Experiments with the clean tube system built for the 12 inch wafer shows the validity of the proposed model and the algorithm.

실리콘 웨이퍼 연삭 가공의 기구학적 모델링과 해석 (Kinematic Modeling and Analysis of Silicon Wafer Grinding Process)

  • 김상철;이상직;정해도
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2002년도 춘계학술대회 논문집
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    • pp.42-45
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    • 2002
  • General wheel mark in mono-crystalline silicon wafer finding is able to be expected because it depends on radius ratio and angular velocity ratio of wafer and wheel. The pattern is predominantly determined by the contour of abrasive grits resulting from a relative motion. Although such a wheel mark is made uniform pattern if the process parameters are fixed, sub-surface defect is expected to be distributed non-uniformly because of characteristic of mono-crystalline silicon wafer that has diamond cubic crystal. Consequently it is considered that this phenomenon affects the following process. This paper focused on kinematic analysis of wafer grinding process and simulation program was developed to verify the effect of process variables on wheel mark. And finally, we were able to predict sub-surface defect distribution that considered characteristic of mono-crystalline silicon wafer

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클린튜브 시스템의 웨이퍼 정지 제어 (Wafer Motion Control of a Clean Tube System)

  • 신동헌;최철환
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2003년도 춘계학술대회 논문집
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    • pp.459-462
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    • 2003
  • This paper presents a force model of the clean tube system, which was developed as a means for transferring the air-floated wafers inside the closed tube filled with the super clean air. The recovering force from the holes for floating wafers is modeled as a linear spring and thus the wafer motion is modeled as a mass-spring-damper system. The propelling forces are modeled as linear along with the wafer location. The paper also proposes the control method to emit and stop a wafer at the center of a control unit. It shows the minimum value of the propelling force to leave from the control unit. In order to stop the wafer, it utilizes the exact time when a wafer arrives at the position to activate the propelling force. Experiments with the clean tube system built for 12 inch wafer shows the validity of the proposed model and the algorithm.

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Overview of High Performance 3D-WLP

  • Kim, Eun-Kyung
    • 한국재료학회지
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    • 제17권7호
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    • pp.347-351
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    • 2007
  • Vertical interconnect technology called 3D stacking has been a major focus of the next generation of IC industries. 3D stacked devices in the vertical dimension give several important advantages over conventional two-dimensional scaling. The most eminent advantage is its performance improvement. Vertical device stacking enhances a performance such as inter-die bandwidth improvements, RC delay mitigation and geometrical routing and placement advantages. At present memory stacking options are of great interest to many industries and research institutes. However, these options are more focused on a form factor reduction rather than the high performance improvements. In order to improve a stacked device performance significantly vertical interconnect technology with wafer level stacking needs to be much more progressed with reduction in inter-wafer pitch and increases in the number of stacked layers. Even though 3D wafer level stacking technology offers many opportunities both in the short term and long term, the full performance benefits of 3D wafer level stacking require technological developments beyond simply the wafer stacking technology itself.

CMP 공정에서의 웨이퍼 연마 불균일성에 대한 유한요소해석 연구 (Study on Within-Wafer Non-uniformity Using Finite Element Method)

  • 양우열;성인하
    • Tribology and Lubricants
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    • 제28권6호
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    • pp.272-277
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    • 2012
  • Finite element analysis was carried out using wafer-scale and particle-scale models to understand the mechanism of the fast removal rate(edge effect) at wafer edges in the chemical-mechanical polishing process. This is the first to report that a particle-scale model can explain the edge effect well in terms of stress distribution and magnitude. The results also revealed that the mechanism could not be fully understood by using the wafer-scale model, which has been used in many previous studies. The wafer-scale model neither gives the stress magnitude that is sufficient to remove material nor indicates the coincidence between the stress distribution and the removal rate along a wafer surface.

반도체 웨이퍼용 스크라이빙 머신의 파라메터 결정 (The Parameter Determination of a Scribing Machine for Semiconductor Wafer)

  • 차영엽;최범식
    • 한국정밀공학회지
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    • 제20권2호
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    • pp.218-225
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    • 2003
  • The general dicing process cuts a semiconductor wafer to lengthwise and crosswise direction by using a rotating circular diamond blade. However, inferior goods may be made under the influence of several parameters in dicing process such as blade, wafer, cutting water and cutting conditions. Moreover we can not apply this dicing method to a GaN wafer, because the GaN wafer is harder than other wafers such as SiO$_2$, GaAs, GaAsP, and AlGaAs. In order to overcome this problem, development of a new dicing process and determination of dicing parameters are necessary. This paper describes determination of several parameters - scribing depth, scribing force, scriber inclined angle, scribing speed, and factor for scriber replacement - for a new dicing machine using a scriber.

웨이퍼 연마용 지능형 연삭시스템 개발 (Development of the intelligent grinding system for wafer grinding)

  • 김동석;최춘규;하상백;이상직
    • 대한기계학회:학술대회논문집
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    • 대한기계학회 2004년도 춘계학술대회
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    • pp.1082-1086
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    • 2004
  • In silicon wafer manufacturing process, the grinding process has been adopted to improve the flatness of wafer. The grinding of wafer is usually used by the infeed grinding machine. The infeed grinding machine has been depended on imports. Therefore, it is necessary to develop the infeed grinding machine because the demand of the infeed grinding machine is increasing more and more. This paper describes the technologies of infeed grinding machine and intend to introduce the studies in the development of the intelligent grinding system for grinding of wafer. The air bearing spindle for the infeed grinding machine was developed by domestic technologies and the grinding part design of the intelligent grinding system for wafer grinding was completed.

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실리콘 웨이퍼 습식 식각장치 설계 및 공정개발 (Design of Single-wafer Wet Etching Bath for Silicon Wafer Etching)

  • 김재환;이용일;홍상진
    • 반도체디스플레이기술학회지
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    • 제19권2호
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    • pp.77-81
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    • 2020
  • Silicon wafer etching in micro electro mechanical systems (MEMS) fabrication is challenging to form 3-D structures. Well known Si-wet etch of silicon employs potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH) and sodium hydroxide (NaOH). However, the existing silicon wet etching process has a fatal disadvantage that etching of the back side of the wafer is hard to avoid. In this study, a wet etching bath for 150 mm wafers was designed to prevent back-side etching of silicon wafer, and we demonstrated the optimized process recipe to have anisotropic wet etching of silicon wafer without any damage on the backside. We also presented the design of wet bath for 300 mm wafer processing as a promising process development.

Cu CMP 공정중 Wafer 표면의 알루미나 연마입자의 점착 (Adhesion of Alumina Slurry Particles on Wafer Surfaces during Cu CMP)

  • 홍의관;박진구
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.2
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    • pp.1292-1295
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    • 2004
  • 본 연구는 Cu CMP공정 중 알루미나 연마입자의 wafer 표면에서의 점착과 오염을 AFM (Atomic Force Microscopy)을 사용하여 슬러리내에서 점착력 측정과 실제 연마 후 wafer 표면의 오염을 실험적으로 비교 평가하였다. 연마입자의 adhesionn force 측정에 있어서도 역시 wafer들의 zetapotential 결과와 잘 일치하였으며, 모든 wafer 종류에 관계없이, 산성 영역에서 염기성영역의 슬러리가 적용됨에 따라 adhesion force가 작아짐을 확인할 수 있었다. 특히 FSG wafer의 zetapotential 결과는 비록 산성 분위기에서는 양성 전하값을 나타내었으나, 염기성 분위기의 pH에서는 급격하게 음성 전하값을 나타내었고, 이는 adhesionn force결과와 FESEM 결과와 잘 일치하였다.

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Wafer Packing Box 안정화 설계 (Design Alterations of a Packing Box for the Semiconductor Wafer to Improve Stability)

  • 윤재훈;허장욱;이일환
    • 반도체디스플레이기술학회지
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    • 제21권1호
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    • pp.62-66
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    • 2022
  • Semiconductor is one of the most internationally competitive areas among domestic industries, the major concern of which is the stability of the wafer manufacturing processes. The packaging process is the final step in wafer manufacturing. Problems in the wafer packaging process cause large losses. The vibrations are supposed to be the most important factors for the packaging quality. In this study, the structure of a packaging box was analyzed through experiments and computer simulations, and further the effects of design alterations to suppress the vibrations have been investigated. The final result shows that the vibrations can be reduced substantially to improve the stability of the structure.