• Journal of the Semiconductor & Display Technology
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• v.11 no.2
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• pp.33-38
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• 2012

The wafer positioning robot in the semiconductor industry is required to operate at high speed for the improvement of productivity. The residual vibration caused by the high speed of the wafer positioning robot, however, makes the life of the robot shorter and the cycle time longer. In this study, the input shaping and the path of the system are designed for the reduction of the residual vibration and the improvement of the cycle time. The followings are the process for the reduction and the improvement; 1) System modeling of the wafer positioning robot, 2) Verification of dynamic characteristics of the wafer positioning robot, 3) Input shaping plan using impulse response reiteration, 4) Simulation test using SIMULINK program, 5) Analysis of result.

• Particle and aerosol research
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• v.14 no.2
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• pp.41-47
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• 2018

Numerical analysis was conducted to characterize particle deposition onto a heated horizontal semiconductor wafer in vacuum environment. In order to calculate the properties of gas surrounding the wafer, the gas was assumed to obey the ideal gas law. Particle transport mechanisms considered in the present study were convection, Brownian diffusion, gravitational settling and thermophoresis. Averaged particle deposition velocities on the upper surface of the wafer were calculated with respect to particle size, based on the numerical results from the particle concentration equation in the Eulerian frame of reference. The deposition velocities were obtained for system pressures of 1000 Pa~1 atm, wafer heating of 0~5 K and particle sizes of $2{\sim}10^4nm$. The present numerical results showed good agreement with the available experimental ones.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.5
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• pp.365-371
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• 2003

We prepared silicon on insulator(SOI) wafer pairs of Si/1800${\AA}$ -SiO$_2$ ∥ 1800${\AA}$ -SiO$_2$/Si using water direct bonding method. Wafer pairs bonded at room-temperature were annealed by a normal furnace system or a fast linear annealing(FLA) equipment, and the micro-structure of bonding interfaces for each annealing method was investigated. Upper wafer of bonded pairs was polished to be 50 $\mu\textrm{m}$ by chemical mechanical polishing(CMP) process to confirm the real application. Defects and bonding area of bonded water pairs were observed by optical images. Electrical and mechanical properties were characterized by measuring leakage current for sweeping to 120 V, and by observing the change of wafer curvature with annealing process, respectively. FLA process was superior to normal furnace process in aspects of bonding area, I-V property, and stress generation.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.1
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• pp.94-98
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• 2012

The behavior of ozone micro bubble cleaning system was investigated to evaluate the solution as a new method of solar cell wafer cleaning in comparison with former conventional RCA cleaning. We have developed the ozone dissolution system in the ozonated water for more efficient cleaning conditions. The optimized cleaning conditions for solar cell wafer process were 10 ppm of ozone concentration and 12 minutes in cleaning periods, respectively. We have confirmed the cleaning reliability and cell efficiencies after ozone micro bubble cleaning. Using this new cleaning technology, it was possible to obtain higher efficiency, higher productivity, and fast tact time for applying cleaning in the fields on bare ingot wafer, LED wafers as well as the solar cell wafer.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.3 s.96
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• pp.78-83
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• 1999

The bonding interface is dependent on the properties of surfaces prior to SDB(silicon wafer direct bonding). In this paper, we prepared silicon surfaces in several chemical solutions, and annealed bonding wafers which were combined with thermally oxidized wafers and bare silicon wafers in the temperature range of $600{\times}1000^{\circ}C$. After bonding, the bonding interface is investigated by an infrared(IR) topography system which uses the penetrability of infrared through silicon wafer. Using this procedure, we observed intrinsic bubbles at elevated temperatures. So, we verified that these bubbles are related to cleaning and drying conditions, and the interface oxides on silicon wafer reduce the formation of intrinsic bubbles.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.29 no.1 s.232
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• pp.96-106
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• 2005

An integrated single-wafer processing tool, composed of multiple single wafer processing modules, transfer robots, and load locks, has complex routing sequences, and often has critical post-processing residency constraints. Scheduling of these tools is an intricate problem, and testing schedulers with actual tools requires too much time and cost. The Single Wafer Processor (SWP) simulator presented in this paper is to validate an on-line scheduler, and evaluate performance of integrated single-wafer processing tools before the scheduler is actually deployed into real systems. The data transfer between the scheduler and the simulator is carried out with TCP/IP communication using messages and files. The developed simulator consists of six modules, i.e., GUI (Graphic User Interface), emulators, execution system, module managers, analyzer, and 3D animator. The overall framework is built using Microsoft Visual C++, and the animator is embodied using OpenGL API (Application Programming Interface).

• Transactions of the Korean Society of Mechanical Engineers
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• v.18 no.1
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• pp.175-183
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• 1994

To investigate thermophoretic effect on particle deposition, average deposition velocity toward a horizontal wafer surface in vertical airflow is measured keeping the wafer surface temperature different from the surrounding air temperature. In the present measurement, the temperature difference is maintained in the range from -10 to $4^{\circ}$ C Polystyrene latex (PSL) spheres of diameter between 0.3 and 0.8 .mu.m are used for the experiment. The number of particles deposited on a wafer surface is estimated from the measurements using a wafer surface scanner (PMS SAS-3600). Experimental data are compared with prediction model results.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2005.11a
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• pp.559-563
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• 2005

The wafer positioning robot used in the semiconductor industry is required to operate at high speed for the improvement of productivity. However, the residual vibration produced by the high speed of the wafer positioning robot makes the life of the robot shorter and the cycle time longer. In this study, the input shaping and the path of the system are designed for the reduction of the residual vibration and the optimization of the cycle time. The followings are the process for the reduction and the optimization; 1)System modeling of wafer positioning robot, 2)Verification of dynamic characteristic of wafer positioning robot, 3)Input shaping plan using impulse response reiteration, 4)Simulation test using simulink, 6)Analysis of result.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.509-510
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• 2013

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.06a
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• pp.541-542
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• 2008