• Journal of Korean Society of Industrial and Systems Engineering
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• v.39 no.1
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• pp.73-80
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• 2016

This study focuses on the formation of input release lots in a semiconductor wafer fabrication facility. After the order-lot pegging process assigns lots in the fab to orders and calculates the required quantity of wafers for each product type to meet customers' orders, the decisions on the formation of input release lots should be made to minimize the production costs of the release lots. Since the number of lots being processed in the wafer fab directly is related to the productivity of the wafer fab, the input lot formation is crucial process to reduce the production costs as well as to improve the efficiency of the wafer fab. Here, the input lot formation occurs before every shift begins in the semiconductor wafer fab. When input quantities (of wafers) for product types are given from results of the order-lot pegging process, lots to be released into the wafer fab should be formed satisfying the lot size requirements. Here, the production cost of a homogeneous lot of the same type of product is less than that of a heterogeneous lot that will be split into the number of lots according to their product types after passing the branch point during the wafer fabrication process. Also, more production cost occurs if a lot becomes more heterogeneous. We developed a multi-dimensional dynamic programming algorithm for the input lot formation problem and showed how to apply the algorithm to solve the problem optimally with an example problem instance. It is necessary to reduce the number of states at each stage in the DP algorithm for practical use. Also, we can apply the proposed DP algorithm together with lot release rules such as CONWIP and UNIFORM.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.176-180
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• 2001

There are several factors causing re-work in CMP process such as improper polish time calculation by operator. removal rate decline of the polisher, unstable in-suit pad conditioning, slurry supply module problem and wafer carrier rotation inconsistancy. And conclusively those fundimental reason for the re-work rate increasement is mainly from the cycle time delay between wafer polish and post measurement. Therefore, Wafer thickness measurement in wet condition could be able to remove those improper process conditions which may happen during the process in comparison with the conventional dried wafer measurement system and it can be able to reduce the CMP process cycle time. CMP scrap reduction by overpolish, re-work rate reduction, thickness control efficiency also can be easily achieved. CMP Equipment manufacturer also trying to develop integrated system which has multi-head & platen, cleaner, pre & post thickness measure and even control the polish time from the calculated removal rate of each polishing head by software. CMP re-work problem such as over & under polish by target thickness may result in the cycle time delay. By reducing those inefficient factors during the process and establish of the automatic process control, CLC system need to be adopted to maximize the process performance. Wafer to Wafer Polish Time Feed Back Control by measuring the wafer right after the polish shorten the polish time calculation for the next wafer and it lead to the perfact Post CMP target thickness control capability. By Monitoring all of the processed the wafer, CMP process will also be stabilize itself.

• Journal of Korea Foundry Society
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• v.33 no.2
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• pp.69-74
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• 2013

Silicon (Si) wafer was grown by using direct growth from Si melt and contaminations of wafer during the process were investigated. In our process, BN was coated inside of all graphite parts including crucible in system to prevent carbon contamination. In addition, coated BN layer enhance the wettability, which ensures the favorable shape of grown wafer by proper flow of Si melt in casting mold. As a result, polycrystalline silicon wafer with dimension of $156{\times}156$ mm and thickness of $300{\pm}20$ um was successively obtained. There were, however, severe contaminations such as BN and SiC on surface of the as-grown wafer. While BN powders were easily removed by brushing surface, SiC could not be eliminated. As a result of BN analysis, C source for SiC was from binder contained in BN slurry. Therefore, to eliminate those C sources, additional flushing process was carried out before Si was melted. By adding 3-times flushing processes, SiC was not detected on the surface of as-grown Si wafer. Polycrystalline Si wafer directly grown from Si melt in this study can be applied for the cost-effective Si solar cells.

• Journal of Digital Contents Society
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• v.5 no.4
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• pp.251-256
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• 2004

The flatness of a silicon wafer concerned with ULSI chip is one of the most critical parameters ensuring high yield of wafers. That is necessary to constitute the circuit with high quality for he surface of silicon wafer, which comes to be base to make the direct circuit of the semiconductor, Flatness, therefore, is the most important factor to guarantee it wafer with high quality. The process of polishing is one of the most crucial production line among 10 processing stages to change the rough surface into the flatnees with best quality. Currently at this process, it is general for an engineer in charge to observe, judge and control the model of wafer from the monitor of measuring equipment with his/her own eyes to enhance the degree of flatness. This, however, is quite a troublesome job for someone has to check of process by one's physical experience. The purpose of this study is to approach the model of wafer with digital contents and to apply the result of the research for an algorithm which enables to control the polishing process by means of measuring the degree of flatness automatically, not by person, but by system. In addition, this paper shows that this algorithm proposed for the whole wafer flatness enables to draw an estimated algorithm which is for the thickness of sites to measure the degree of flatness for each site of wafer.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.71-74
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• 2013

In this study, the effects of wafer warpage on the misalignment during wafer stacking process were investigated. The wafer with $45{\mu}m$ bow height warpage was purposely fabricated by depositing Cu thin film on a silicon wafer and the bonding misalignment after bonding was observed to range from $6{\mu}m$ to $15{\mu}m$. This misalignment could be explained by a combination of $5{\mu}m$ radial expansion and $10{\mu}m$ linear slip. The wafer warpage seemed to be responsible for the slip-induced misalignment instead of radial expansion misalignment.

• Korean Journal of Materials Research
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• v.25 no.1
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• pp.16-20
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• 2015

In this study, in order to improve the efficiency of n-type monocrystalline solar cells with an Alu-cell structure, we investigate the effect of the amount of Al paste in thin n-type monocrystalline wafers with thicknesses of $120{\mu}m$, $130{\mu}m$, $140{\mu}m$. Formation of the Al doped $p^+$ layer and wafer bowing occurred from the formation process of the Al back electrode was analyzed. Changing the amount of Al paste increased the thickness of the Al doped $p^+$ layer, and sheet resistivity decreased; however, wafer bowing increased due to the thermal expansion coefficient between the Al paste and the c-Si wafer. With the application of $5.34mg/cm^2$ of Al paste, wafer bowing in a thickness of $140{\mu}m$ reached a maximum of 2.9 mm and wafer bowing in a thickness of $120{\mu}m$ reached a maximum of 4 mm. The study's results suggest that when considering uniformity and thickness of an Al doped $p^+$ layer, sheet resistivity, and wafer bowing, the appropriate amount of Al paste for formation of the Al back electrode is $4.72mg/cm^2$ in a wafer with a thickness of $120{\mu}m$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.176-180
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• 2001

There are several factors causing re-work in CMP process such as improper polish time calculation by operator, removal rate decline of the polisher, unstable in-suit pad conditioning, slurry supply module problem and wafer carrier rotation inconsistency. And conclusively those fundimental reason for the re-work rate increasement is mainly from the cycle time delay between wafer polish and post measurement. Therefore, Wafer thickness measurement in wet condition could be able to remove those improper process conditions which may happen during the process in comparison with the conventional dried wafer measurement system and it can be able to reduce the CMP process cycle time. CMP scrap reduction by overpolish, re-work rate reduction, thickness control efficiency also can be easily achieved. CMP Equipment manufacturer also trying to develop integrated system which has multi-head & platen, cleaner, pre & post thickness measure and even control the polish time from the calculated removal rate of each polishing head by software. CMP re-work problem such as over & under polish by target thickness may result in the cycle time delay. By reducing those inefficient factors during the process and establish of the automatic process control, CLC system need to be adopted to maximize the process performance. Wafer to Wafer Polish Time Feed Back Control by measuring the wafer right after the polish shorten the polish time calculation for the next wafer and it lead to the perfect Post CMP target thickness control capability. By Monitoring all of the processed the wafer, CMP process will also be stabilize itself.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.22 no.1
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• pp.168-172
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• 2013

In 3D wafer-stacking technology, one of the major issues is wafer warpage. Especially, The important reason of warpage has been known due to CTE(Coefficient of Thermal Expansion) mismatch between materials. It was too hard to choose how to make the FE model for blanket structured wafer level 3D packaging, because the thickness of each layer in wafer level 3D packaging was too small (micro meter or nano meter scale) comparing with diameter of wafer (6 or 8 inches). In this study, the FE model using the shell element was selected and simulated by the ANSYS WorkBench to investigate effects of the CTE on the warpage. To verify the FE model, it was compared by experimental results.

• Journal of Sensor Science and Technology
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• v.15 no.5
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• pp.341-346
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• 2006

We have fabricated SOI CMOS active pixel image sensor with the pinned photodiode on handle wafer in order to reduce dark currents and improve spectral response. The structure of the active pixel image sensor is 4 transistors APS which consists of a reset and source follower transistor on seed wafer, and is comprised of the photodiode, transfer gate, and floating diffusion on handle wafer. The source of dark current caused by the interface traps located on the surface of a photodiode is able to be eliminated, as we apply the pinned photodiode. The source of dark currents between shallow trench isolation and the depletion region of a photodiode can be also eliminated by the planner process of the hybrid bulk/SOI structure. The photodiode could be optimized for better spectral response because the process of a photodiode on handle wafer is independent of that of transistors on seed wafer. The dark current was about 6 pA at 3.3 V of floating diffusion voltage in the case of transfer gate TX = 0 V and TX=3.3 V, respectively. The spectral response of the pinned photodiode was observed flat in the wavelength range from green to red.