• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.55-60
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• 2020

The hard mask photo-resist strip inspection system for the semiconductor wafer manufacturing process inspects the position of the circuit pattern formed on the wafer by measuring the distance from the edge of the wafer to the strip processing area. After that, it is an inspection system that enables you to check the process status in real time. Process defects can be significantly reduced by applying a tester that has not been applied to the existing wafer strip process, edge etching process, and wafer ashing process. In addition, it is a technology for localizing semiconductor process inspection equipment that can analyze the outer diameter of the wafer and the state of pattern formation, which can secure process stability and improve wafer edge yield.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.427-431
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• 2005

In this study, 6' GaAs wafer bonding system is designed and optimized to bond 6 inches device wafer and material wafer. Bonding process is performed in vacuum environment and resin is used to bond two wafers. Vacuum module and double heating mechanisms are adopted to minimize wafer warpage and void. Structure and heat transfer analysis, et al of the core modules review the designed mechanisms are very effective in performance improvement. As a result, high productivity (tack time cut-down) and stabilized process can be obtained by reducing breakage failure of wafer.

• Journal of Industrial Technology
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• v.43 no.1
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• pp.49-55
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• 2023

Cluster tools are extensively employed in various wafer fabrication processes within the semiconductor manufacturing industry, including photo lithography, etching, and chemical vapor deposition. Contemporary fabrication facilities encounter customer orders with technical specifications that are similar yet slightly varied. Consequently, modern fabrications concurrently manufacture two or three different wafer types using a cluster tool to maximize chamber utilization and streamline the flow of wafer lots between different process stages. In this review, we introduce two methods of concurrent processing of multiple wafer types: 1) concurrent processing of multiple wafer types with different job flows, 2) concurrent processing of multiple wafer types with identical job flows. We describe relevant research trends and achievements and discuss future research directions.

• Journal of Korean Institute of Industrial Engineers
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• v.29 no.2
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

• Korean Journal of Materials Research
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• v.24 no.12
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• pp.682-688
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• 2014

Physical and chemical changes in a polished wafer and in $2.5{\mu}m$ & $4{\mu}m$ epitaxially grown Si layer wafers (Epilayer wafer) after surface treatment were investigated. We characterized the influence of surface treatment on wafer properties such as surface roughness and the chemical composition and bonds. After each surface treatment, the physical change of the wafer surface was evaluated by atomic force microscopy to confirm the surface morphology and roughness. In addition, chemical changes in the wafer surface were studied by X-ray photoemission spectroscopy measurement. Changes in the chemical composition were confirmed before and after the surface treatment. By combined analysis of the physical and chemical changes, we found that diluted hydrofluoric acid treatment is more effective than buffered oxide etching for $SiO_2$ removal in both polished and Epi-Layer wafers; however, the etch rate and the surface roughness in the given treatment are different among the polished $2.5{\mu}m$ and $4{\mu}m$ Epi-layer wafers in spite of the identical bulk structural properties of these wafers. This study therefore suggests that independent surface treatment optimization is required for each wafer type, $2.5{\mu}m$ and $4{\mu}m$, due to the meaningful differences in the initial surface chemical and physical properties.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.19 no.3
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• pp.22-28
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• 2020

This paper investigates the effects of retaining ring materials, particularly PPS and PEEK, used in the CMP process, on wafer polishing and ring wear. CMP can be performed using bonded type retaining rings made with PPS or injection molding type retaining rings made with PEEK. In this study, after polishing a wafer with a PPS retaining ring, the average profile height of the wafer was 0.098 ㎛ less than that of the wafer polished with a PEEK retaining ring, implying that PPS retaining rings achieve a higher polishing rate. In addition, the center area of the wafer profile had less deviation and improved flatness after polishing with the PPS ring. These results indicate that a higher polishing rate and smaller profile height deviation can be achieved using retaining rings made with PPS compared to retaining rings made with PEEK. Therefore, with semiconductor circuit patterns becoming finer and wafer sizes becoming larger, the use of PPS in CMP retaining rings can obtain more stable wafer polishing results compared to that of PEEK.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.1
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• pp.1-5
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• 2013

Wafer-to-Wafer (W2W) integration technology is an emerging technology promising many benefits, such as reduced size, improved performance, reduced power, lower cost, and divergent integration. As the maturity of W2W technology progresses, new applications will become more viable. However, at present the cost for W2W integration is still very high and both manufacturing yield and reliability issues have not been resolved yet for high volume manufacturing (HVM). Especially for WTW integration resolving compound yield issue can be a key factor for HVM. To have the full benefits of WTW integration technology more than simple wafer stacking technologies are necessary. In this paper, the manufacturing yield for W2W integration is described and the challenges of WTW integration will be discussed.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.6
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• pp.148-155
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• 2008

This study presents a process control of the wafer edge exposure (WEE) used in 300[mm] wafer environment. WEE, as a key module of the overall track system (coater and developer) for making patterns on wafer, is a system to expose the UV-ray on the wafer to remove a photo resist around edge of the wafer. It can measure, memorize and control the distance and angles from wafer center to edge. Recently in the 300[mm] semiconductor fabrication, the track system strongly requires that WEE station has a controller with high throughput and accuracy to increase process efficiency. We have designed and developed the controller, and present here a WEE control algorithm and experimental results.

• Journal of the Semiconductor & Display Technology
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• v.16 no.3
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• pp.1-7
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• 2017

Multi-wafer planetary type chemical vapor deposition reactors are widely used in thin film growth and suitable for large scale production because of the high degree of growth rate uniformity and process reproducibility. In this study, a two-dimensional model for estimating the effect of the gap between satellite and wafer on the wafer surface temperature distribution is developed and analyzed using computational fluid dynamics technique. The simulation results are compared with the results obtained from an analytical method. The simulation results show that a drop in the temperature is noticed in the center of the wafer, the temperature difference between the center and wafer edges is about $5{\sim}7^{\circ}C$ for all different ranges of the gap, and the temperature of the wafer surface decreases when the size of the gap increases. The simulation results show a good agreement with the analytical ones which is based on one-dimensional heat conduction model.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.629-632
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• 1998

This paper presents a new and simple technique to realize high Q inductor on low resistivity silicon wafer with 6 $\Omega$.cm. This technique is very compatible with bipolar and CMOS standard silicon process. By forming the deep and narrow trenches on the low resistivity wafer substrate under inductor pattern, oxidizing and filling with undoped polysilicon, the low resistivity silicon wafer acts as high resistivity wafer being suitable for the fabrication of high Q inductor. By using this technique the quality factor (Q) for 8-turn spiral inductor was improved up to max. 10.3 at 2 ㎓ with 3.0 $\mu\textrm{m}$ of metal thickness. The experiment results show that Q on low resistivity silicon wafer with the trench technique have been improved more than 2 times compared to the conventional low resistivity silicon wafer without trenches.