• Title/Summary/Keyword: WAFER

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Development of the intelligent grinding system for wafer grinding (웨이퍼 연마용 지능형 연삭시스템 개발)

  • Kim, Dong-Seok;Choi, Chun-Kyu;Ha, Sang-Baek;Lee, Sang-Jik
    • Proceedings of the KSME Conference
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    • pp.1082-1086
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    • 2004
  • In silicon wafer manufacturing process, the grinding process has been adopted to improve the flatness of wafer. The grinding of wafer is usually used by the infeed grinding machine. The infeed grinding machine has been depended on imports. Therefore, it is necessary to develop the infeed grinding machine because the demand of the infeed grinding machine is increasing more and more. This paper describes the technologies of infeed grinding machine and intend to introduce the studies in the development of the intelligent grinding system for grinding of wafer. The air bearing spindle for the infeed grinding machine was developed by domestic technologies and the grinding part design of the intelligent grinding system for wafer grinding was completed.

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Design of Single-wafer Wet Etching Bath for Silicon Wafer Etching (실리콘 웨이퍼 습식 식각장치 설계 및 공정개발)

  • Kim, Jae Hwan;Lee, Yongil;Hong, Sang Jeen
    • Journal of the Semiconductor & Display Technology
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    • v.19 no.2
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    • pp.77-81
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    • 2020
  • Silicon wafer etching in micro electro mechanical systems (MEMS) fabrication is challenging to form 3-D structures. Well known Si-wet etch of silicon employs potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH) and sodium hydroxide (NaOH). However, the existing silicon wet etching process has a fatal disadvantage that etching of the back side of the wafer is hard to avoid. In this study, a wet etching bath for 150 mm wafers was designed to prevent back-side etching of silicon wafer, and we demonstrated the optimized process recipe to have anisotropic wet etching of silicon wafer without any damage on the backside. We also presented the design of wet bath for 300 mm wafer processing as a promising process development.

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Adhesion of Alumina Slurry Particles on Wafer Surfaces during Cu CMP (Cu CMP 공정중 Wafer 표면의 알루미나 연마입자의 점착)

  • Hong, Yi-Koan;Park, Jin-Goo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • pp.1292-1295
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    • 2004
  • 본 연구는 Cu CMP공정 중 알루미나 연마입자의 wafer 표면에서의 점착과 오염을 AFM (Atomic Force Microscopy)을 사용하여 슬러리내에서 점착력 측정과 실제 연마 후 wafer 표면의 오염을 실험적으로 비교 평가하였다. 연마입자의 adhesionn force 측정에 있어서도 역시 wafer들의 zetapotential 결과와 잘 일치하였으며, 모든 wafer 종류에 관계없이, 산성 영역에서 염기성영역의 슬러리가 적용됨에 따라 adhesion force가 작아짐을 확인할 수 있었다. 특히 FSG wafer의 zetapotential 결과는 비록 산성 분위기에서는 양성 전하값을 나타내었으나, 염기성 분위기의 pH에서는 급격하게 음성 전하값을 나타내었고, 이는 adhesionn force결과와 FESEM 결과와 잘 일치하였다.

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Wafer Motion Control of a Clean Tube System (클린튜브 시스템의 웨이퍼 정지 제어)

  • 신동헌;최철환
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • pp.459-462
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    • 2003
  • This paper presents a force model of the clean tube system, which was developed as a means for transferring the air-floated wafers inside the closed tube filled with the super clean air. The recovering force from the holes for floating wafers is modeled as a linear spring and thus the wafer motion is modeled as a mass-spring-damper system. The propelling forces are modeled as linear along with the wafer location. The paper also proposes the control method to emit and stop a wafer at the center of a control unit. It shows the minimum value of the propelling force to leave from the control unit. In order to stop the wafer, it utilizes the exact time when a wafer arrives at the position to activate the propelling force. Experiments with the clean tube system built for 12 inch wafer shows the validity of the proposed model and the algorithm.

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Overview of High Performance 3D-WLP

  • Kim, Eun-Kyung
    • Korean Journal of Materials Research
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    • v.17 no.7
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    • pp.347-351
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    • 2007
  • Vertical interconnect technology called 3D stacking has been a major focus of the next generation of IC industries. 3D stacked devices in the vertical dimension give several important advantages over conventional two-dimensional scaling. The most eminent advantage is its performance improvement. Vertical device stacking enhances a performance such as inter-die bandwidth improvements, RC delay mitigation and geometrical routing and placement advantages. At present memory stacking options are of great interest to many industries and research institutes. However, these options are more focused on a form factor reduction rather than the high performance improvements. In order to improve a stacked device performance significantly vertical interconnect technology with wafer level stacking needs to be much more progressed with reduction in inter-wafer pitch and increases in the number of stacked layers. Even though 3D wafer level stacking technology offers many opportunities both in the short term and long term, the full performance benefits of 3D wafer level stacking require technological developments beyond simply the wafer stacking technology itself.

Study on Within-Wafer Non-uniformity Using Finite Element Method (CMP 공정에서의 웨이퍼 연마 불균일성에 대한 유한요소해석 연구)

  • Yang, Woo Yul;Sung, In-Ha
    • Tribology and Lubricants
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    • v.28 no.6
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    • pp.272-277
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    • 2012
  • Finite element analysis was carried out using wafer-scale and particle-scale models to understand the mechanism of the fast removal rate(edge effect) at wafer edges in the chemical-mechanical polishing process. This is the first to report that a particle-scale model can explain the edge effect well in terms of stress distribution and magnitude. The results also revealed that the mechanism could not be fully understood by using the wafer-scale model, which has been used in many previous studies. The wafer-scale model neither gives the stress magnitude that is sufficient to remove material nor indicates the coincidence between the stress distribution and the removal rate along a wafer surface.

The Parameter Determination of a Scribing Machine for Semiconductor Wafer (반도체 웨이퍼용 스크라이빙 머신의 파라메터 결정)

  • 차영엽;최범식
    • Journal of the Korean Society for Precision Engineering
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    • v.20 no.2
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    • pp.218-225
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    • 2003
  • The general dicing process cuts a semiconductor wafer to lengthwise and crosswise direction by using a rotating circular diamond blade. However, inferior goods may be made under the influence of several parameters in dicing process such as blade, wafer, cutting water and cutting conditions. Moreover we can not apply this dicing method to a GaN wafer, because the GaN wafer is harder than other wafers such as SiO$_2$, GaAs, GaAsP, and AlGaAs. In order to overcome this problem, development of a new dicing process and determination of dicing parameters are necessary. This paper describes determination of several parameters - scribing depth, scribing force, scriber inclined angle, scribing speed, and factor for scriber replacement - for a new dicing machine using a scriber.

A Study on the Master Controller System for Detecting a Failure of the WAFER (불량 WAFER을 검출하기 위한 마스터 콘트롤러 시스템에 관한 연구)

  • Kim, Hyo-Nam
    • Proceedings of the Korean Society of Computer Information Conference
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    • pp.1-4
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    • 2015
  • 현재 고해상도 디스플레이 제품 생산은 대량 생산 공정 시스템으로 가동하고 있으며, 대량 생산 과정에서 WAFER의 제작 불량률을 낮추는 것이 생산업체에서 무엇보다도 주요한 목표이며 이와 함께 불량 제품을 정확하고 빠르게 검출하는 것이 매우 중요하다. 본 논문에서는 불량 WAFER을 정확하게 검출하기 위한 검출시스템으로 멀티 포인트 온도 검출 방법으로 구현된 면적형 온도 센서 기능과 검출된 데이터를 유/무선 통신방식으로 상위의 관리/모니터링 시스템으로 전송 할 수 있는 기능을 가진 마스터 콘트롤러 시스템을 제안한다.

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A Study on the Realtime Monitoring System of the WAFER PROCESS (WAFER PROCESS 실시간 모니터링 시스템에 관한 연구)

  • Kim, Hyo-Nam
    • Proceedings of the Korean Society of Computer Information Conference
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    • pp.297-298
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    • 2015
  • 반도체 제조 및 FPD제조 공정 중 WAFER 및 GLASS 제품의 상태를 직접적으로 관리하는 기술로서 기존에 널리 사용하고 있는 방법은 CHAMBER의 온도나 상태 등의 설비 컨디션 상태를 관리 모니터링 하는 것이다. 반도체 제조의 공정비용을 최소화하기 위하여 기존 방법과 달리 WAFER 및 GLASS의 온도 상태 등을 직접적으로 모니터링 하는 시스템으로 반도체 FPD제조 공정 중 장비의 개별 특성에 따라 제품의 공정 편차로 인해 발생되는 공정불량을 실시간으로 모니터링함으로서 불량을 최소화 할 수 있는 시스템을 제안한다.

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A study on the real-time monitoring & control for wafer fabrication process (웨이퍼 가공공정 실시간 감시제어에 관한 연구)

  • 임성호;이근영;이범렬;한근희;최락만
    • 제어로봇시스템학회:학술대회논문집
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    • pp.421-426
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    • 1989
  • Many of semiconductor manufacturing companies persuit automation of wafer fabrication to improve the yields and quality of their products. Development of real-time control system for wafer fabrication and wafer/cassette automatic transfer-system is the most important part to achieve the purpose. In this paper, SECS protocol proposed by SEMI is briefly reviewed and an implementation method of real-time monitoring and control system is suggested as one of the possible ways for wafer fabrication automation. The system consists of process equipments supporting SECS.

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