• Transactions of the Korean Society of Mechanical Engineers B
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• v.30 no.4 s.247
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• pp.306-313
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• 2006

Automated material handling system is being used as a method to reduce manufacturing cost in the semiconductor and flat panel displays (FPDs) manufacturing process. Those are considering switch-over from the traditional cassette system to single-substrate transfer system to reduce raw materials of stocks in the processing line. In the present study, the wafer transportation speed has been evaluated by numerical and experimental method for three propulsion nozzle array (face, front, rear) in an air levitation system. Test facility for 300 mm wafer was equipped with two control tracks and a transfer track of 1,500mm length. The diameter of propulsion nozzle is 0.8mm and air velocity of wafer propulsion is $50\sim150m/s$. We found that the experimental results of the wafer transportation speed were well agreed with the numerical ones. Namely, the predicted values of the maximum wafer transportation speed are higher than those values of experimental data by 16% and the numerical result of the mean wafer transportation speed is higher than the experimental result within 20%.

• Journal of the Semiconductor & Display Technology
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• v.12 no.4
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• pp.39-44
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• 2013

In the semiconductor heat-treatment process, the temperature uniformity determines the film quality of a wafer. This film quality effects on the overall yield rate. The heat transfer of the wafer surface in the heat-treatment process equipment is occurred by convection and radiation complexly. Because of this, there is the nonlinearity between the wafer temperature and reactor. Therefore, the accurate prediction of temperature on the wafer surface is difficult without the direct measurement. The thermal camera and the T/C wafer are general ways to confirm the temperature uniformity on the heat-treatment process. As above ways have limit to measure the temperature in the precise domain under the micro-scale. In this study, we developed the thin film type temperature sensor using the MEMS technology to establish the system which can measure the temperature under the micro-scale. We combined the experiment and numerical analysis to verify and calibrate the system. Finally, we measured the temperature on the wafer surface on the semiconductor process using the developed system, and confirmed the temperature variation by comparison with the commercial T/C wafer.

• Journal of the Korean Wood Science and Technology
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• v.15 no.1
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• pp.12-21
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• 1987

본질(本質) Cement board제조(製造)를 위하여 지금까지 톱밥, 목편(木片) 및 목수(木手)(excelsior)가 사용되어 왔으나, Wafer를 사용한 제품(製品)은 아직 개발(開發)되지 않고 있는 실정이다. 따라서, 본(本) 연구(硏究)는 Cement wafer board를 압력별(壓力別), Wafer 길이별(別), Cement와 목재(木材)의 배합비별(配合比別), Wafer 배열별(排列別)로 제조(製造)하여 그 영향인자(影響因子)를 조사(調査)하고 이에 따른 제품(製品)의 물리적(物理的), 기계적(機械的) 성질(性質)을 구명(究明)하고자 실시(實施)하였으며 다음과 같은 결론(結論)을 얻었다. 1. Cement Wafer board 제품(製品)의 적정압력(壓力)은 30kg/$cm^2$이었고, 30kg/$cm^2$ 이상(以上)의 압에서는 board의 기계적 성질에 나쁜 영향을 미쳤다. 2. Cement와 목재(木材)의 배합비(配合比)가 2.1을 넘을 경우에는 board의 성질에 나쁜 영향을 끼쳤다. 3. 한쪽 방향(方向)으로 Cement-Wafer가 배열된 조건에서 제조된 CWB가 최고의 곡강도(曲强度)를 나타내었다. 4. CWB의 곡강도(曲强度)는 다른 목질(木質) Cement board보다 높은 값을 나타내었으나 박리강도(剝離强度)에 있어서는 목편 Cement board보다 약간 낮은 값을 나타내었다. 5. CWB의 난연성(難燃性) 시험(試驗)은 난연3급(難燃3級)을 만족시켰다.

• Korean Journal of Computational Design and Engineering
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• v.19 no.3
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• pp.214-223
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• 2014

This paper presents a bottleneck detection framework using simulation approach in a wafer FAB (Fabrication). In a semiconductor manufacturing industry, wafer FAB facility contains various equipment and dozens kinds of wafer products. The wafer FAB has many characteristics, such as re-entrant processing flow, batch tools. The performance of a complex manufacturing system (i.e. semiconductor wafer FAB) is mainly decided by a bottleneck. This paper defines the problem of a bottleneck process and propose a simulation based framework for bottleneck detection. The bottleneck is not the viewpoint of a machine, but the viewpoint of a step with the highest WIP in its upstream buffer and severe fluctuation. In this paper, focus on the classification of bottleneck steps and then verify the steps are not in a starvation state in last, regardless of dispatching rules. By the proposed framework of this paper, the performance of a wafer FAB is improved in on-time delivery and the mean of minimum of cycle time.

• Journal of the Semiconductor & Display Technology
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• v.18 no.3
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• pp.82-87
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• 2019

One of the most critical aspects of the semiconductor industry is the quality of the wafer surface. And the vibrations of wafer grinder are supposed to be the most dominant factors to damage the wafer surface quality. In this study, structure of a wafer grinder has been analyzed through experiments and computer simulations to figure out the main reasons of the vibrations. And the design alterations based on the analysis were applied to identify the effects of those alterations on the vibration suppression. The result shows that the design alterations can effectively suppress about 90% of the vibrations.

• Journal of the Semiconductor & Display Technology
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• v.8 no.1
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• pp.1-5
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• 2009

Typically, single-wafer wet etching is done by dispensing chemical onto the front and back side of spin wafer. The wafer is fixed by a number of chuck pins, which obstruct the chemical flow and would result in the incomplete removal of the remaining film, which can become a source of contamination in the next process. In this paper, we introduce a novel design of wafer chuck, in which chuck pins are groupped into two and each group of pins fixes the substrate alternatively. Two groups of chuck pins fix the high-speed spin substrate with non contact method using a magnetic material. The actual process has been executed to observe the effectiveness of this new wafer chuck. It was found that the new wafer chuck performed better than the conventional wafer chuck for removing the remaining film from the bevel and edge side of substrate.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.29-33
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• 2012

The demand for 3D wafer level integration has been increasing significantly. Although many technical challenges of wafer stacking are still remaining, wafer stacking is a key technology for 3D integration due to a high volume manufacturing, smaller package size, low cost, and no need for known good die. Among several new process techniques Cu-to-Cu wafer bonding is the key process to be optimized for the high density and high performance IC manufacturing. In this study two main challenges for Cu-to-Cu wafer bonding were evaluated: misalignment and bond quality of bonded wafers. It is demonstrated that the misalignment in a bonded wafer was mainly due to a physical movement of spacer removal step and the bond quality was significantly dependent on Cu bump dishing and oxide erosion by Cu CMP.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.81-85
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• 2013

Wafer stacking technology becomes more important for the next generation IC technology. It requires new process development such as TSV, wafer bonding, and wafer thinning and also needs to resolve wafer warpage, power delivery, and thermo-mechanical reliability for high volume manufacturing. In this study, Cu CMP which is the key process for wafer bonding has been studied using Cu CMP and oxide CMP processes. Wafer samples were fabricated on 8" Si wafer using a damascene process. Cu dishing after Cu CMP and oxide CMP was $180{\AA}$ in average and the total height from wafer surface to bump surface was approximately $2000{\AA}$.

• Transactions of the Korean Society of Mechanical Engineers
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• v.19 no.5
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• pp.1319-1332
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• 1995

Numerical analysis was performed to characterize the particle deposition behavior on a horizontal free-standing wafer with thermophoretic effect under the turbulent flow field. A low Reynolds number k-.epsilon. turbulence model was used to analyze the turbulent flow field around the wafer, and the temperature field for the calculation of the thermophoretic effect was predicted from the energy equation introducing the eddy diffusivity concept. The deposition mechanisms considered were convection, diffusion, sedimentation, turbulence and thermophoresis. For both the upper and lower surfaces of the wafer, the averaged particle deposition velocities and their radial distributions were calculated and compared with the laminar flow results and available experimental data. It was shown by the calculated averaged particle deposition velocities on the upper surface of the wafer that the deposition-free zone, where the deposition velocite is lower than 10$^{-5}$ cm/s, exists between 0.096 .mu.m and 1.6 .mu.m through the influence of thermophoresis with positive temperature difference of 10 K between the wafer and the ambient air. As for the calsulated local deposition velocities, for small particle sizes d$_{p}$<0.05 .mu.m, the deposition velocity is higher at the center of the wafer than at the wafer edge, whereas for particle size of d$_{p}$ = 2.0 .mu.m the deposition takes place mainly on the inside area of the wafer. Finally, an approximate model for calculating the deposition velocities was recommended and the calculated deposition velocity results were compared with the present numerical solutions, those of Schmidt et al.'s model and the experimental data of Opiolka et al.. It is shown by the comparison that the results of the recommended model agree better with the numerical solutions and Opiolka et al.'s data than those of Schmidt's simple model.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.22 no.1
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• pp.321-326
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• 2021

This paper presents a technique to minimize damaged wafers during loading. A thin wafer used in solar cells and semiconductors can be damaged easily. This makes it difficult to separate the wafer due to surface tension between the loaded wafers. A technique for minimizing damaged wafers is to supply compressed air to the wafer and simultaneously apply a small horizontal movement mechanism. The main experimental factors used in this study were the supply speed of wafers, the nozzle pressure of the compressed air, and the suction time of a vacuum head. A higher supply speed of the wafer under the same nozzle pressure and lower nozzle pressure under the same supply speed resulted in a higher failure rate. Furthermore, the damage rate, according to the wafer supply speed, was unaffected by the suction time to grip a wafer. The optimal experiment conditions within the experimental range of this study are the wafer supply speed of 600 ea/hr, nozzle air pressure of 0.55 MPa, and suction time of 0.9 sec at the vacuum head. In addition, the technology improved by the repeatability performance tests can minimize the damaged wafer rate.