• Title/Summary/Keyword: WSI

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Effect of WSi$_2$ Gate Electrode on Thin Oxide Properties in MOS Device (MOS 소자에서 WSi$_2$ 게이트 전극이 Thin Oxide 성질에 미치는 영향)

  • 박진성;이현우;김갑식;문종하;이은구
    • Journal of the Korean Ceramic Society
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    • v.35 no.3
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    • pp.259-263
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    • 1998
  • WSi2/CVD-Si/SiO2/Si-substrate의 폴리사이드 구조에서 실리콘 증착 POCl3 확산 그리고 WSi2 증착 유무에 따른 Thin oxide 특성을 연구했다 WSi2 막을 증착하지 않은 CVD-Si/SiO2/Si-substrate 구조에서 CVD-Si을 po-lycrystalline-Si으로 증착한 시편이 amorphous-Si을 증착한 시편보다 산화막 불량이 적다 WSi2 를 증착시킨 WSi2/CVD-Si/SiO2./Si-substrate의 구조에서 CVD-Si의 polycrystalline-Si 혹든 amorphous-Si 의 막 증착에 따른 thin oxide의 불량율 차이는 미미하다 산화막 불량은 CVD-Si에 확산시킨 인(P) 증가 즉 면저항(sheet resistance) 감소로 증가한다. Thin oxide의 절연특성은 WSi2 증착으로 저하된다 WSi2 증착으로 산화막 두께는 증가하나 막 특성은 열등해져 산화막 절연성이 떨어진다.

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Effects of annealing on the properties of $WSi_x$ films in ploycide structure formed by LPCVD method (Polycide구조로 저압화학증착된 $WSi_x$박막의 열처리에 따른 거동)

  • 이재호;임호빈;이종무
    • Electrical & Electronic Materials
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    • v.3 no.4
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    • pp.263-270
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    • 1990
  • WSi$_{x}$박막을 Polycide구조로 저압화학증착법에 의해 제작한 후, 열처리를 N$_{2}$분위기에서 30분간 여러온도로 수행하였다. WSi$_{x}$박막의 전기비저항은 열처리온도의 증가에 따라 감소하였으며 1000.deg.C이상으로 열처리한 시편의 경우, 하부 다결정실리콘층의 도우핑여부에 관계없이 35.mu.m.OMEGA.-cm 정도를 나타내었다. 560.deg.C의 열처리에서 WSi$_{x}$박막은 정방정의 WSi$_{2}$ 결정질로 결정화가 되기 시작하였고 열처리온도의 증가에 따라 WSi$_{2}$결정립의 성장도 관찰되었다. 열처리온도에 따른 전기저항의 변화는 WSi$_{x}$박막의 결정립크기와 밀접한 관계가 있었다. 증착된 WSi$_{x}$박막내의 광잉실리콘원자들이 열처리중에 하부의 다결정실리콘층으로 재분배됨을 AES분석에 의해 확인하였다. Hall 측정결과 900.deg.C이상으로 열처리된 시편은 Hole도전체의 거동을 나타내었고 800.deg.C이하로 열처리된 시편은 electron도전체의 거동을 나타내었다.

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Effects of $WSi_x$, thickness and F concentration on gate oxide characteristics in tungsten polycide gate structure (Tungsten polycide gate 구조에서 $WSi_x$ 두께와 fluorine 농도가 gate oxide 특성에 미치는 영향)

  • 김종철
    • Journal of the Korean Vacuum Society
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    • v.5 no.4
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    • pp.327-332
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    • 1996
  • In this study, the effects of $WSi_x$, thickness and fluorine concentration in tungsten polycide gate structure on gate oxide were investigated. As $WSi_x$, thickness increases, gate oxide thickness increases with fluorine incorporation in gate oxide, and time-to-breakdown($T_{BD,50%}$) of oxide decreases. The stress change with $WSi_x$ thickness was also examined. But it is understood that the dominant factor to degrade gate oxide properties is not the stress but the fluorine, incorporated during $WSi_x$ deposition, diffused into $WSiO_2$ after heat treatment. In order to understand the effect of fluorine diffusion into oxidem fluorine ion implanted gates were compared. The thickness variation and $T_{BD,50%}$ of gate oxide is saturated over 600 $\AA$ thickness of $WSi_x$. The TEM and SIMS studies show the microstructure less than 600 $\AA$ thickness is dense and flat in surface. However, over 600$\AA$, the microstructure of $WSi_x$ is divided into two parts: upper porous phase with rugged surface and lower dense phase with smmoth interface. And this upper phase is transformed into oxygen rich crystalline phase after annealing, and the fluorine is captured in this layer. Therefore, the fluorine diffusion into the gate oxide is saturated.

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Characteristics of Gate Electrode for WSi2/CVD-Si/SiO2 (WSi2/CVD-Si/SiO2 구조의 게이트 전극 특성)

  • 박진성;정동진;이우성;이예승;문환구;김영남;손민영;이현규;강성철
    • Journal of the Korean Ceramic Society
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    • v.30 no.1
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    • pp.55-61
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    • 1993
  • In the WSi2/CVD-Si/SiO2 polycide structure, electrode resistance and its property were studied as a function of deposition temperature and thickness of CVD-Si, diffusion condition of POCl3, and WSi2 being deposited or not. Resistivity of poly-Si is decreased with increment of thickness in the case of POCl3 diffusion of low sheet resistance, but it is increased in the case of high sheet resistance. The resistivity of amorphous-Si is generally lower than that of poly-Si. Initial sheet resistance of poly-Si/WSi2 gate electrode is affected by the thickness and resistance of poly-Si layer, but final resistance after anneal, 900$^{\circ}C$/30min/N2, is only determined by WSi2 layer. Flourine diffuses into SiO2, but tungsten does not. In spite of out-diffusion of phosphorus into WSi2 layer, the sheet resistance is not changed.

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Optical Probe of white Light Interferometry for Precision Coordinate Metrology (정밀 삼차원 측정을 위한 백색광 간섭 광학 프로브 개발)

  • 김승우;진종한;강민구
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2002.05a
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    • pp.195-198
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    • 2002
  • Demand for high precision measurement of large area is increasing in many industrial fields. White-light Scanning Interferometer(WSI) is a well-known method for 3D profile measurement. However WSI has some limitations in a measurement range because of the sensing mechanism. Therefore, in this paper we use a heterodyne laser interferometer to get over the limitations of a short measurement range in WSI, We suggest a new WSI system combined with heterodyne laser interferometer. This system is aimed at eliminating Abbe error with measuring the focus point directly. With the use of triggering functionality of WSI, we can use this system as a probe of a precision stage such as a probe of CMM. The suggested system gives a repeatability of 87 nm in the absolute distance measurement test under the laboratory environment.

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Electrical Properties of Annealed $WSi_{x}$ Films Deposited on P+ Polysilicon by LPCVD (P+ Polysilicon층 위에 저압화학증착된 $WSi_{x}$ 박막의 열처리에 따른 전기적 특성)

  • 이희승;임호빈;이종무
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1990.10a
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    • pp.81-85
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    • 1990
  • $WSi_{x}$ film deposited on p+ polysilicon by low pressure chemical vapor deposition method were annealed by rapid thermal process, their properties have been investigated by measurements of electrical resistivity and Hall voltage and by analyses of phases and microstructure using X-ray diffraction and SEM technique. The electrical resistivity of the polycides consisting of the tungsten silicide and the p+ polysilicon decreases with the increase in annealing temperature due probably to the increase in grain size. unlike the polycides consisting of the $WSi_{x}$ and n+ polysilicon, however, the Hall voltage of the polycides consisting of $WSi_{x}$ and p+ polysilicon were positive for all specimens annealed as well as the as-deposited one, indicating the majority carrier in $WSi_{x}$. is hole and is independent of the annealing.

Deposition of Spacer-Si3N4 Thin Film for WSi2 Word-Line and Bit-Line (WSi2 word-line 및 bit-line용 spacer-Si3N4 박막의 증착)

  • Ahn S.;Kim D.W.;Kim J.H;Ahn S.J.;Kim Y.J.;Kim H.S.
    • Korean Journal of Materials Research
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    • v.14 no.6
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    • pp.402-406
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    • 2004
  • $WSi_2$, $TiSi_2$, $CoSi_2$, and $TaSi_2$ are general silicides used today in semiconductor devices. $WSi_2$ thin films have been proposed, studied and used recently in CMOS technology extensively to reduce sheet resistance of polysilicon and $n^{+}$ region. However, there are several serious problems encountered because $WSi_2$ is oxidized and forms a native oxide layer at the interface between $WSi_2$ and $Si_3$$N_4$. In this study, we have introduced 20 $slm-N_2$ gas from top to bottom of the furnace in order to control native oxide films between $WSi_2$ and $Si_3$$N_4$ film. In resulting SEM photographs, we have observed that the native oxide films at the surface of $WSi_2$ film are removed using the long injector system.

Tungsten Silicide ($WSi_2$) for Alternate Gate Metal in Metal-Oxide-Semiconductor (MOS) Devices (금속-산화막-반도체 소자에서 대체 게이트 금속인 텅스텐 실리사이드의 특성 분석)

  • 노관종;윤선필;양성우;노용한
    • Proceedings of the IEEK Conference
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    • 2000.06b
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    • pp.64-67
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    • 2000
  • Tungsten silicide(WSi$_2$) is proposed for the alternate gate electrode of ULSI MOS devices. Good structural property and low resistivity of WSi$_2$ deposited by a low pressure chemical vapor deposition(LPCVD) method directly on SiO$_2$ is obtained after annealing. Especially, WSi$_2$-SiO2 interface remains flat after annealing tungsten silicide at high temperature. Electrical characteristics of annealed WSi$_2$-SiO$_2$-Si(MOS) capacitors were improved in view of charge trapping.

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