• Proceedings of the Korean Information Science Society Conference
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• 2011.06b
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• pp.416-419
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• 2011

본 논문에서는 XILINX의 합성 과정에서 생성되는 XDL 설계 데이터를 분석해서, 그로부터 verilog 네트리스트를 생성하는 소프트웨어의 개발에 관한 내용이다. 이 소프트웨어는 XILINX 용 P&R 소프트웨어, 논리 합성 소프트웨어의 개발, 또는 FPGA 상에서 특정 컴포넌트의 위치를 파악해냄으로써 FPGA 상에서 SEU 오류의 위치를 검출하는데 보조적으로 사용할 수 있다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.655-658
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• 2016

Xilinx 7-Series FPGA(Field Programmable Gate Array)s mainly used for the implementation of high-performance digital circuit have SRAM-type configuration memory and can malfunction when soft errors occur in their configuration memory. SEM(Soft Error Mitigation Controller) offered by Xilinx helps users mitigate the influence of soft errors in configuration memory. When soft errors occur, SEM Controller can recover the state of FPGA through partial reconfiguration if the soft errors are correctable by ECC(Error Correction Code) and CRC(Cyclic Redundancy Code). This paper presents the availability analysis of Xilinx 7-Series FPGAs against soft errors under the protection of the SEM Controller. Availability functions are derived and compared according to the correction capability of the SEM Controller. The result may help to estimate the reliability of SRAM-based FPGA running in an environment where soft errors may occur.

• The Journal of Korean Association of Computer Education
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• v.16 no.3
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• pp.99-105
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• 2013

The FPGA-based emulation is an essential step in ASIC design for validation. For emulation with maximal frequency, it is crucial to understand the FPGA characteristics. This paper attempts to analyze the performance characteristics of the modern FPGAs from renowned vendors, Xilinx and Altera, with a case study utilizing various adders and MIPS CPU. Unlike the common wisdom, ripple-carry adder (RCA) does not utilize the inherent carry-chain inside FPGAs when structurally designed based on 1-bit adders. Thus, the RCA shows the inferior performance to the other types of adders in FPGAs. Our study also reveals that FPGAs from Xilinx exhibit different characteristics from the ones from Altera. That is, the prefix adder, which is optimized for speed in ASIC design, shows the poor performance on Xilinx devices, whereas it provides a comparable speed to the IP core on Altera devices. It suggests that error-prone manual change of the original design can be avoided on Altera devices if area is permitted. Experiments with MIPS CPU confirm the arguments.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.12
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• pp.1667-1674
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• 2018

Recently, speeding up real time calculation using the specialized hardware accelerator is often used in the various engineering and science area, and the accelerators are required to include PCI express interconnection between FPGA and a host computer. The implementation of the high speed PCIe for the multi-giga bytes per second transmission is one of the most difficult issue in the development of the accelerators. There are several commercialized IP solutions and research results in the literature, but these solutions are required extra cost and design period to analyze the detailed implementation method. For the hardware accelerator on Xilinx FPGA, utilizing Xilinx's XDMA PCIe IP, which is provided without extra charge, can be the best solution in terms of the development period and cost. Consequently, this paper presents the evaluation system on Zynq-7000 FPGA and Windows 10 host computer, and analyze the performance of the PCIe IP with various configuration parameters.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.9
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• pp.1803-1810
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• 2009

This paper designed IQ imbalance estimator and compensator to cancel the IQ imbalance error in DVB-T system using OFDM by Matlab. Among Matlab model, we designed and implemented IQ imbalance estimator and compensator by System Generator of Xilinx and Matlab model compared with Xilinx System Generator Model for FPGA implementation. As a result of simulation, we confirmed that both model estimated and compensated IQ imbalance error very well. Also, we verified the performance through hardware co-simulation, timing analysis and resource estimation with Xilinx Spartan3 xc3s1000 fg676-4 target Device.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.36 no.8
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• pp.816-823
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• 2008

This paper describes the test results of developed high speed data processing unit using Xilinx GTP(Multi-Gigabit-Transceiver) interface and DDR-2 memory. The high speed data processing unit receives input data from packet generator at 1.25Gbps and transmits stored data to the data receiving system at 700Mbps. Therefore, DDR-2 memory controller and Xilinx GTP interface are implemented by FPGA instead of CPU to process high speed data directly.

• Proceedings of the KAIS Fall Conference
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• 2003.06a
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• pp.250-252
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• 2003

본 논문에서는 콘벌루션 부호를 사용한 대역확산 방식의 디지틀 통신모뎀을 FPGA를 이용하여 설계 및 검증을 하였다. 대역확산 방식에서의 콘벌루tus부호기(K=3, R=1/2), PN code(128chip) generator와 비터비 디코더를 Xilinx사의 FPGA 디자인 툴인 Xilinx Foundations3.1을 사용하여 VHDL simulation과 timing simulation을 수행하였고, FPGA 회로설계 검증 장비인 EDA-Lab 3000 장비를 사용하여 Xilinx사의 SPARTAN2 2S100PQ208칩에 configuration 한 후 Agilent사의 1681A logic analyzer를 사용하여 설계된 회로의 동작을 검증하였다.

• Proceedings of the Korea Information Assurance Society Conference
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• 2004.05a
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• pp.59-64
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• 2004

In this paper a design and an implementation of a crypto chip which implements SEED and Triple-DES algorithms are described. We designed it by VHDL(VHSIC Hardware Description Language) which is a designed system-description language. To apply the chip to various application, four operating Modes such as ECB, CBC, CFB, and CFB are supported. The chip was designed by the Virtex-E XCV2000E BG560 of Xilinx and we confirmed result of it at the FPGA implementation by functional and timing simulation using the Xilinx Foundation Series 3.li.

• Proceedings of the Korea Information Processing Society Conference
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• 2019.10a
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• pp.60-62
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• 2019

지능형 IoT 애플리케이션들을 효과적으로 사용하기 위해서는 추론 엔진을 Edge device로 포팅하는 것이 필수적이다. 그러나 컴퓨팅 자원이 제한적인 Edge 환경에서 computational cost가 상당히 큰 CNN 추론을 실시간으로 하는 것은 쉽지 않다. 이에, CNN 추론의 하드웨어 가속화의 필요성이 제기되어 활발한 연구가 진행되고 있으며, Xilinx, Intel 등에서도 하드웨어 가속화를 도와주는 툴을 개발하여 지속적으로 업그레이드하고 있다. 본 연구에서는 CIFAR-10 데이터베이스의 테스트 이미지 10,000개를 Xilinx 사의 CNN 추론 엔진인 DPU를 사용하여 Zynq UltraScale+ 보드에서 추론해보고, DPU 아키텍처에 따른 결과를 비교·분석했다. 병렬처리 수준을 높게 한 DPU는 그렇지 않은 DPU보다 소비전력 및 자원 사용량이 3배 이상 높았지만, 1.65배 좋은 성능을 보여 Trade-off 관계를 확인할 수 있었다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.5
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• pp.906-911
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• 2008

This paper designed Simulik Model to cancel the carrier frequency offset in OFDM using CORDIC Algorithm and evaluated its performance. And Simulink Model compared with Xilinx System Generator Model for FPGA implementation. As a result of simulation, we confirmed that both model is error free by CORDIC when offset frequency is lower than $10^5MHz$. Also, we verified the performance through Hardware Co-simulation with Xilinx Spartan3 xc3s1000 fg676-4 Target Device, and timing analysis and resource estimation.