• Title/Summary/Keyword: address decoding

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Joint Virtual User Identification and Channel Security En/Decoding Method for Ad hoc Network

  • Zhang, Kenan;Li, Xingqian;Ding, Kai;Li, Li
    • International Journal of Computer Science & Network Security
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    • v.22 no.11
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    • pp.241-247
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    • 2022
  • Ad hoc network is self-organized network powered by battery. The reliability of virtual user identification and channel security are reduced when SNR is low due to limited user energy. In order to solve this problem, a joint virtual user identification and channel security en/decoding method is proposed in this paper. Transmitter-receiver-based virtual user identification code is generated by executing XOR operation between orthogonal address code of transmitter and pseudo random address code of receiver and encrypted by channel security code to acquire orthogonal random security sequence so as to improve channel security. In order to spread spectrum as well as improve transmission efficiency, data packet is divided into 6-bit symbols, each symbol is mapped with an orthogonal random security sequence. Subspace-based method is adopted by receiver to process received signal firstly, and then a judgment model is established to identify virtual users according to the previous processing results. Simulation results indicate that the proposed method obtains 1.6dB Eb/N0 gains compared with reference methods when miss alarm rate reaches 10-3.

VLSI design of efficient VLC/VLD utilizing the characteristics of MPEG DCT coefficients (MPEG DCT 계수의 특징을 이용한 효율적인 VLC/VLD의 VLSI 설계)

  • Kong, Jong-Pil;Kim, Young-Min
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.33B no.1
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    • pp.79-86
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    • 1996
  • In this paper we propose an architecture for VLC(Variable Length Coder) and VLD(Variable Length Decoder) which is simple with respect to implementation point and efficient in memory. We implemented encoding and decoding circuit where we need only 7-bit address memory space for 114 MPEG1 DCT coefficients and employed minimal number of flip-flops and logics for an architecture to integrate a shift register for serial-to-parallel or parallel-to-serial conversion of the data in code mapping ROM. We obtained 50Mbps operating speed in both encoding and decoding process as the result of simulation using 0.80.8${\mu}m$ CMOS standard cells.

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Approaching Near-Capacity on a Multi-Antenna Channel using Successive Decoding and Interference Cancellation Receivers

  • Sellathurai, Mathini;Guinand, Paul;Lodge, John
    • Journal of Communications and Networks
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    • v.5 no.2
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    • pp.116-123
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    • 2003
  • In this paper, we address the problem of designing multirate codes for a multiple-input and multiple-output (MIMO) system by restricting the receiver to be a successive decoding and interference cancellation type, when each of the antennas is encoded independently. Furthermore, it is assumed that the receiver knows the instantaneous fading channel states but the transmitter does not have access to them. It is well known that, in theory, minimummean- square error (MMSE) based successive decoding of multiple access (in multi-user communications) and MIMO channels achieves the total channel capacity. However, for this scheme to perform optimally, the optimal rates of each antenna (per-antenna rates) must be known at the transmitter. We show that the optimal per-antenna rates at the transmitter can be estimated using only the statistical characteristics of the MIMO channel in time-varying Rayleigh MIMO channel environments. Based on the results, multirate codes are designed using punctured turbo codes for a horizontal codedMIMOsystem. Simulation results show performances within about one to two dBs of MIMO channel capacity.

A Design of Parallel Turbo Decoder based on Double Flow Method Using Even-Odd Cross Mapping (짝·홀 교차 사상을 이용한 Double Flow 기법 기반 병렬 터보 복호기 설계)

  • Jwa, Yu-Cheol;Rim, Chong-Suck
    • Journal of the Institute of Electronics and Information Engineers
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    • v.54 no.7
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    • pp.36-46
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    • 2017
  • The turbo code, an error correction code, needs a long decoding time since the same decoding process must be repeated several times in order to obtain a good BER performance. Thus, parallel processing may be used to reduce the decoding time, in which case there may be a memory contention that requires additional buffers. The QPP interleaving has been proposed to avoid such case, but there is still a possibility of memory contention when a decoder is constructed using the so-called double flow technique. In this paper, we propose an even-odd cross mapping technique to avoid memory conflicts even in decoding using the double-flow technique. This method uses the address generation characteristic of the QPP interleaving and can be used to implement the interleaving circuit between the decoding blocks and the LLR memory blocks. When the decoder implemented by applying the double flow and the proposed methods is compared with the decoder by the conventional MDF techniques, the decoding time is reduced by up to 32% with the total area increase by 8%.

Special Memory Design for Graphics (그래픽스 전용 메모리 설계)

  • 김성진;문상호
    • Journal of Korea Multimedia Society
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    • v.2 no.1
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    • pp.80-88
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    • 1999
  • In this paper, we propose a Special Memory for Graphics(SMGRA) which accelerates memory access time for graphics operations. The SMGRA has a rectangular array memory architecture which has already proposed by Whelan to process pixels in the rectangle area simultaneously, but the SMGRA should improve address decoding time and reduce the number of address pins by using address multiplexing scheme. The SMGRA has a Z-value comparator in the DRAM which is to convert read-modify-write Z buffer into single-write only operation that improves approximately 50% frame buffer access bandwidth.

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Exploiting Quality Scalability in Scalable Video Coding (SVC) for Effective Power Management in Video Playback (계층적 비디오 코딩의 품질확장성을 활용한 전력 관리 기법)

  • Jeong, Hyunmi;Song, Minseok
    • KIISE Transactions on Computing Practices
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    • v.20 no.11
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    • pp.604-609
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    • 2014
  • Decoding processes in portable media players have a high computational cost, resulting in high power consumption by the CPU. If decoding computations are reduced, the power consumed by the CPU is also be reduced, but such a choice generally results in a degradation of the video quality for the users, so it is essential to address this tradeoff. We proposed a new CPU power management scheme that can make use of the scalability property available in the H.164/SVC standard. We first proposed a new video quality model that makes use of a video quality metric(VQM) in order to efficiently take into account the different quantization factors in the SVC. We then propose a new dynamic voltage scaling(DVS) scheme that can selectively combine the previous decoding times and frame sizes in order to accurately predict the next decoding time. We then implemented a scheme on a commercial smartphone and performed a user test in order to examine how users react to the VQM difference. Real measurements show that the proposed scheme uses up to 34% fewer energy than the Linux DVFS governor, and user tests confirm that the degradation in the quality is quite tolerable.

The Presentation of Semi-Random Interleaver Algorithm for Turbo Code (터보코드에 적용을 위한 세미 랜덤 인터리버 알고리즘의 제안)

  • Hong, Sung-Won;Park, Jin-Soo
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.2
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    • pp.536-541
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    • 2000
  • Turbo code has excellent decoding performance but had limitations for real time communications because of the system complexity and time delay in decoding procedure. To overcome this problem, a new SRI(Semi-Random Interleaver) algorithm which realize the reduction of the interleaver size is proposed for reducing the time delay during the decoding prodedure. SRI compose the interleaver 0.5 size from the input data sequence. In writing the interleaver, data is recorded by row such as block interleaver. But, in reading, data is read by randomly and the text data is located by the just address simultaneously. Therefore, the processing time of with the preexisting method such as block, helical random interleaver.

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An efficient search of binary tree for huffman decoding based on numeric interpretation of codewords

  • Kim, Byeong-Il;Chang, Tae-Gyu;Jeong, Jong-Hoon
    • Proceedings of the IEEK Conference
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    • 2002.07a
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    • pp.133-136
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    • 2002
  • This paper presents a new method of Huffman decoding which gives a significant improvement of processing efficiency based on the reconstruction of an efficient one-dimensional array data structure incorporating the numeric interpretation of the accrued codewords in the binary tree. In the Proposed search method, the branching address is directly obtained by the arithematic operation with the incoming digit value eliminating the compare instruction needed in the binary tree search. The proposed search method gives 30% of improved Processing efficiency and the memory space of the reconstructed Huffman table is reduced to one third compared to the ordinary ‘compare and jump’ based binary tree. The experimental result with the six MPEG-2 AAC test files also shows about 198% of performance improvement compared to those of the widely used conventional sequential search method.

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A New Multimedia Service Transmit Method using IPv6 (IPv6를 이용한 새로운 멀티미디어 서비스 전달 방식)

  • Chang, Jeong-Uk;Kim, Ki-Bog;Lin, Chi-Ho
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.1193-1196
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    • 2005
  • In this paper, we presents a new multimedia service transmit method using IPv6. The IPv6 provides the address system of 128 bit and the address space which is infinite it provides. But it will not become the IPv4 and interchange not to be, it uses the DSTM Transition mechanism which will reach and the IPv4 center in the packet header the service type it will be able to support the service class of multi type (TOS) it secures the weak point of data transfer delay it puts a base in the IPv6. The efficiency of this proposed technique have been proven by MPEG-4 streaming video streaming of the IPv6 namely, 6Xtream embodied a order form/live streaming server and the client which it uses to be possible in base and real-time decoding method.

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Near ML Decoding Based on Metric-First Searching and Branch Length Threshold for Multiple Input Multiple Output Systems (여러 입력 여러 출력 시스템에서 길이 먼저 살펴보기와 가지 길이 문턱값을 바탕으로 둔 준최적 복호)

  • An, Tae-Hun;Kang, Hyun-Gu;Oh, Jong-Ho;Song, Iick-Ho;Yoon, Seok-Ho
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.8C
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    • pp.830-839
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    • 2009
  • In this paper, we address a near maximum likelihood (ML) scheme for the decoding of multiple input multiple output systems. Based on the metric-first search method and by employing Schnorr-Euchner enumeration and branch length thresholds, the proposed scheme provides reduced computational complexity. The proposed scheme is shown by simulation to have lower computational complexity than other near ML decoders while maintaining the bit error rate close to the ML performance.