• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.251.1-251.1
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• 2013

Combination of oxidative vacuum annealing and oxygen plasma treatment can serve as a simple and efficient method of line-width modification of imprinted nanopatterns. Since the vacuum annealing and oxygen plasma could lead mass loss of polymeric materials, either one of the process can yield a narrowed patterns. However, the vacuum annealing process usually demands quite high temperatures (${\geq}300^{\circ}C$) and extended annealing time to get appreciable line-width reduction. Although the plasma treatment may be considered as an effective low temperature rapid process for the line-width reduction, it is also suffering for the lowered controllability on application to very fine patterns. We have found that the vacuum annealing temperature can be lowered by introducing the oxygen in the vacuum process and that the combination of oxygen plasma treatment with the vacuum annealing could yield the best result in the line-with reduction of the imprinted polymeric nanopatterns. Well-defined line width reduction by more than 50% was successfully demonstrated at relatively low temperatures. Furthermore, it was verified that this process was applicable to the nanopatterns of different shapes and materials.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.1
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• pp.23-28
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• 2023

This paper demonstrates a novel NAND flash memory structure and annealing configuration including through-silicon via (TSV) inside the silicon substrate to improve annealing efficiency using an electro-thermal annealing (ETA) technique. Compared with the conventional ETA which utilizes WL-to-WL current flow, the proposed annealing method has a higher annealing temperature as well as more uniform heat distribution, because of thermal isolation on the silicon substrate. In addition, it was found that the annealing temperature is related to the electrical and thermal conductivity of the TSV materials. As a result, it is possible to improve the reliability of NAND flash memory. All the results are discussed based on 3-dimensional (3-D) simulations with the aid of the COMSOL simulator.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.11
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• pp.1646-1649
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• 2012

The $O_2$ annealing technique has considerably suppressed the leakage current of GaN power devices, but this forms NiO at Ni-based Schottky contact with increasing on-resistance. The purpose of the present study was to fabricate 1.5 kV GaN Schottky barrier diodes by improving $O_2$-annealing process and GaN buffer. The proposed $O_2$ annealing performed after alloying ohmic contacts in order to avoid NiO construction. The ohmic contact resistance ($R_C$) was degraded from 0.43 to $3.42{\Omega}-mm$ after $O_2$ annealing at $800^{\circ}C$. We can decrease RC by lowering temperature of $O_2$ annealing. The isolation resistance of test structure which indicated the surface and buffer leakage current was significantly increased from $2.43{\times}10^7$ to $1.32{\times}10^{13}{\Omega}$ due to $O_2$ annealing. The improvement of isolation resistance can be caused by formation of group-III oxides on the surface. The leakage current of GaN Schottky barrier diode was also suppressed from $2.38{\times}10^{-5}$ to $1.68{\times}10^{-7}$ A/mm at -100 V by $O_2$ annealing. The GaN Schottky barrier diodes achieved the high breakdown voltage of 700, 1400, and 1530 V at the anode-cathode distance of 5, 10, and $20{\mu}m$, respectively. The optimized $O_2$ annealing and $4{\mu}m$-thick C-doped GaN buffer obtained the high breakdown voltage at short drift length. The proposed $O_2$ annealing is suitable for next-generation GaN power switches due to the simple process and the low the leakage current.

• Journal of Advanced Marine Engineering and Technology
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• v.39 no.1
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• pp.81-85
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• 2015

The organic/inorganic hybrid photovoltaic devices have been studied using Poly(3-hexylthiophene-2,5-diyl) (P3HT) : [6, 6]-Phenyl C61 butyric acid methyl ester (PCBM) and GaN. We traced the effect of short circuit current density with different annealing method under the various concentration and ratio of P3HT:PCBM. During the pre-annealing course, the heat treatments were performed each time at low temperature after the organic layer coated and the samples were heated at high temperature through one or two steps under the post-annealing process. It revealed that the samples with post-annealing process had higher values of short circuit current density than the other samples upon pre-annealing. And the interesting high short circuit current density features were observed at 1:1 mixing ratio and 1wt% of P3HT:PCBM.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.371-372
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• 2012

We have studied lead-based gapless semiconductors, $PbPdO_2$, which is very sensitive to external parameters such as temperature, pressure, electric field, etc[1]. We have fabricated pure $PbPdO_2$, Co- and Mn-doped $PbPdO_2$ thin films using the pulsed laser deposition. Because of the volatile element of Pb, it is very difficult to grow the films. Note that in case of $MgB_2$, Mg is also volatile element. So in order to enhance the quality of $MgB_2$, some experiments are carried out in annealing with Mg-rich atmosphere [2]. This annealing process with volatile element plays an important role in making smooth surface. Thus, we applied such process to our studies of $PbPdO_2$ thin films. As a result, we found the optimal condition of ex-situ annealing temperature ${\sim}650^{\circ}C$ and time ~12 hrs. The ex-situ annealing brought the extreme change of surface morphology of thin films. After ex-situ annealing with PbO-rich atmosphere, the grain size of thin film was almost 100 times enlarged for all the thin films and also the PbO impurity phase was smeared out. And from X-ray diffraction measurements, we determined highly crystallized phases after annealing. So, we measured electrical and magnetic properties. Because of reduced grain boundary, the resistivity of ex-situ annealed samples changed smaller than no ex-situ sample. And the carrier densities of thin films were decreased with ex-situ annealing time. In this case, oxygen vacancies were removed by ex-situ annealing. Furthermore, we will discuss the transport and magnetic properties in pure $PbPdO_2$, Co- and Mn-doped $PbPdO_2$ thin films in detail.

• 대한공업교육학회지
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• v.33 no.1
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• pp.249-264
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• 2008

In this dissertation, shallow $p^+-n$ junctions were formed by ion implantation and dual-step annealing processes and a new simulator is designed to model boron diffusion in silicon. This simulator predicts the boron distribution after ion implantation and annealing. The dopant implantation was performed into the crystalline substrates using $BF_2$ ions. The annealing was performed with a RTA(Rapid Thermal Annealing) and a FA(Furnace Annealing) process. The model which is used in this simulator takes into account nonequilibrium diffusion, reactions of point defects, and defect-dopant pairs considering their charge states, and the dopant inactivation by introducing a boron clustering reaction. FA+RTA annealing sequence exhibited better junction characteristics than RTA+FA thermal cycle from the viewpoint of sheet resistance and the simulator reproduced experimental data successfully. Therefore, proposed diffusion simulator and FA+RTA annealing method was able to applied to shallow junction formation for thermal budget. process.

• Journal of the Korean Society for Heat Treatment
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• v.32 no.2
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• pp.74-78
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• 2019

$Zn_2SnO_4$ thin films were deposited on quartzs substrates by using radio-frequency magnetron sputtering system. Thermal treatments at various temperatures were performed to evaluate the effect of annealing temperatures on the properties of $Zn_2SnO_4$ thin films. Surface morphologies were examined by using field emission-scanning electron microscopy and showed that sizes of grains were slightly increased and grain boundaries were clear with increasing annealing temperatures. The deposited $Zn_2SnO_4$ thin films on quartzs substrates were amorphous structures and no distinguishable crystallographic changes were observed with variations of annealing temperatures. The optical transmittance was improved with increasing annealing temperatures and was over 90% in the wavelength region between 350 and 1100 nm at the annealing temperature of $600^{\circ}C$. The optical energy bandgaps, which derived from the absorbance of $Zn_2SnO_4$ thin films, were increased from 3.34 eV to 3.43 eV at the annealing temperatures of $450^{\circ}C$ and $600^{\circ}C$, respectively. As the annealing temperature was increased, the electron concentrations were decreased. The electron mobility was decreased and resistivity was increased with increasing annealing temperatures with exception of $450^{\circ}C$. These results indicate that heat treatments at higher annealing temperatures improve the optical and electrical properties of rf-sputtered $Zn_2SnO_4$ thin films.

• Current Photovoltaic Research
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• v.10 no.2
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• pp.39-48
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• 2022

A Se-containing Cu/SnSe₂/ZnSe precursor was employed to introduce S to the precursor to form Cu₂ZnSn(S,Se)₄ (CZTSSe) film. The morphology of CZTSSe films strongly varied with two different pre-annealing environments: S and N₂. The CZTSSe film with S pre-annealing showed a dense morphology with a smooth surface, while that with N₂ pre-annealing showed a porous film with a plate-shaped grains on the surface. CuS and Cu₂Sn(S,Se)₃ phases formed during the S pre-annealing stage, while SnSe and Cu₂SnSe₃ phases formed during the N₂ pre-annealing stage. The SnSe phase formed during N₂ pre-annealing generated SnS₂ phase that had plate shape and severely aggravated the morphology of CZTSSe film. The power conversion efficiency of the CZTSSe solar cell with S pre-annealing was low (1.9%) due to existence of Zn(S.Se) layer between CZTSSe and Mo substrate. The results indicated that S pre-annealing of the precursor was a promising method to achieve a good morphology for large area application.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.6
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• pp.582-587
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• 2023

The effects of the annealing temperature on the structural, morphological, and luminescent properties of SrWO₄:Sm³⁺ thin films grown on quartz substrates by radio-frequency magnetron sputtering were investigated. The thin films were annealed at various annealing temperatures for 20 min in a rapid thermal annealer after growing the thin films. The experimental results showed that the annealing temperature has a significant effect on the properties of the SrWO₄:Sm³⁺ thin films. The crystal structure of the as-grown SrWO₄:Sm³⁺ thin films was transformed from amorphous to crystalline after annealing at 800℃. The preferred orientation along (112) plane and a significant increase in average grain size by 820 nm were observed with increasing the annealing temperature. The average optical transmittance in the wavelength range of 500~1,100 nm was decreased from 72.0% at 800℃ to 44.2% at an annealing temperature of 1,000℃, where the highest value in the photoluminescence intensity was obtained. In addition to the red-shift of absorption edge, a higher annealing temperature caused the optical band gap energy of the SrWO₄:Sm³⁺ thin films to fall rapidly. These results suggest that the structural, morphological, and luminescent properties of SrWO₄:Sm³⁺ thin films can be controlled by varying annealing temperature.

• ETRI Journal
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• v.15 no.3
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• pp.1-26
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• 1994

Simulated annealing is an attractive, but expensive, heuristic method for approximating the solution to combinatorial optimization problems. Attempts to parallel simulated annealing, particularly on distributed memory multicomputers, are hampered by the algorithm's requirement of a globally consistent system state. In a multicomputer, maintaining the global state S involves explicit message traffic and is a critical performance bottleneck. To mitigate this bottleneck, it becomes necessary to amortize the overhead of these state updates over as many parallel state changes as possible. By using this technique, errors in the actual cost C(S) of a particular state S will be introduced into the annealing process. This paper places analytically derived bounds on this error in order to assure convergence to the correct optimal result. The resulting parallel simulated annealing algorithm dynamically changes the frequency of global updates as a function of the annealing control parameter, i.e. temperature. Implementation results on an Intel iPSC/2 are reported.