• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.266-269
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• 2012

High-efficiency built-in redundancy analysis (BIRA) is presented. The proposed BIRA uses three techniques to achieve a high repair rate using spare mapping registers with adjustable fault tags to reduce area overhead. Simulation results show that the proposed BIRA is a reasonable solution for embedded memories.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.3
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• pp.287-291
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• 2006

This paper describes mechanical and electric properties of ACSR $410\;mm^2$ conductor from many of older overhead conductor. Samples of conductors itemized two division according to operation sector, green area, salt and pollution area. Samples of conductors operated various environment conditions have undergone laboratory metallurigical investigation and tensile strength torsional ductility and electrical performance. The steel core were found to have retained their original properties to a large degree in both tensile strength and the number of turns to failure. On the other hand the aluminum conductor showed reductions in tensile strength. To determine the remaining useful life of aged conductor, an unacceptable deterioration level has to established for each diagnostic procedure.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.237-243
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• 2012

In recent system-on-chip (SoC) designs, several hundred embedded memory cores have occupied the largest portion of the chip area. Therefore, the yield of SoCs is strongly dependent on the yield of the embedded memory cores. If all memories had built-in self repair (BISR) with optimal repair rates, the area overhead would be very large. A bit-map sharing method using a memory grouping is proposed to reduce the area overhead. Since the bit-map memory occupies the largest portion of the area of the built-in redundancy analysis (BIRA), the proposed bit-map sharing method can greatly reduce the area overhead of the BIRA. Based on the experimental results, the proposed method can reduce the area overhead by about 80%.

• Journal of Sensor Science and Technology
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• v.29 no.1
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• pp.68-73
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• 2020

This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. In this paper, the proposed methodology has been evaluated by a liquid state machine (LSM) for pattern and digit recognition using FPGA and a 0.18 ㎛ CMOS technology with a supply voltage of 1.8 V. the LSM is a neural network (NN) algorithm similar to a spiking neural network (SNN). The experimental results show that the proposed SG-SCL LSM reduced power consumption by 10% compared to the conventional LSM.

• ETRI Journal
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• v.35 no.5
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• pp.808-818
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• 2013

Programmable memory built-in self-test (PMBIST) is an attractive approach for testing embedded memory. However, the main difficulties of the previous works are the large area overhead and low flexibility. To overcome these problems, a new flexible PMBIST (FPMBIST) architecture that can test both single-port memory and dual-port memory using various test algorithms is proposed. In the FPMBIST, a new instruction set is developed to minimize the FPMBIST area overhead and to maximize the flexibility. In addition, FPMBIST includes a diagnostic scheme that can improve the yield by supporting three types of diagnostic methods for repair and diagnosis. The experiment results show that the proposed FPMBIST has small area overhead despite the fact that it supports various test algorithms, thus having high flexibility.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.12
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• pp.177-183
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• 2010

Overhead transmission lines in domestic area have been built by several different design standards of dip and ground clearance. This paper describes an experimental study for evaluating load capacity and dip margin in overhead transmission lines. Such design standards for selection of overhead transmission conductors, dip and ground clearance, as well as electrical equipment technical standard are discussed. Based on daily load and weather data, several characteristics such as line utilization factor, load factor, conductor temperature and dip, etc. are analyzed, and compared with the specified levels of design standards. As a result, it is verified that DLR method can be a clue of the solving of the problem, for occurring in old transmission conductors which may be rarely operating below standards.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.1
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• pp.9-16
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• 2010

This paper presents supervisor control methods at a matrix converter controlled overhead crane system based on a controller area network (CAN). Four induction motors are used to drive the gantry, trolley, and hoist at he crane and each motor is controlled by the matrix converter with direct torque control (DTC). Both the position control algorithm and the supervisor control system using CAN are introduced. Simulation and experimental results are carried out to verify the performance of position control at the matrix converter controlled crane system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.61-68
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• 2004

Today almost all chips have IEEE 1149.1 tap controller inside. Recently the circuit is embedded in the chips for other functional objectives. Hence a CED technique for testing and monitoring the IEEE 1149.1 tap controller had been proposed. This paper studies the optimal CED test technique on the IEEE 1149.1 tap controller. There are duplication, parity prediction, and hybrid techniques. The hybrid technique shows the best result on the area overhead. This means that the hybrid technique is perfectly adequate for the IEEE 1149.1 tap controller to be applied to test with the optimal area overhead and can be used widely in the field. Furthermore, we made more reduction from the previous method resulting in less area overhead.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.1
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• pp.26-33
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• 2013

Femto-cells are low power/cost, micro-base stations and are main components in heterogeneous networks. However, some of technical issues arise when femto-cells are initially installed. One approach to resolve the problems is to control the transmission (TX) power autonomously via SON(Self-Organized Network) scheme. By controlling the femto-cell TX power, the system throughput performance can be improved or the system overhead is highly reduced. Generally, the TX power for maximizing the system throughput and that for reduced system overhead may not be identical. Therefore, we propose a TX power control scheme by which we can improve the system throughput and reduce the system overhead, simultaneously. When we apply the proposed method, the simulation results show that the system overhead can be reduced by up to 41% compared to the performance of the method which maximizes throughput performance only, and the throughput performance can be improved by up to 63% compared to that of the method which only optimizes the coverage area.

• Journal of Korea Society of Industrial Information Systems
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• v.24 no.4
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• pp.9-19
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• 2019

As light-weight embedded devices become widely used in the area of low-power networking and high-precision sensor data acquisition, support for time-critical applications becomes essential for the light-weight embedded devices. This paper addresses the accuracy issue of a software timer for small or tiny embedded devices equiped with light-weight MCUs(Micro controller units). We first explore the characteristics of overhead in a typical implementation of a software timer, and then measure the overhead through a realistic implementation. Using the measurement result, we propose an overhead compensation technique which reduces the overhead from the hardware timer-tick.