• Proceedings of the IEEK Conference
• /
• 2004.06b
• /
• pp.351-354
• /
• 2004

This thesis presents Bipolar transistor with SAVEN(Self-Aligned VErtical Nitride) structure as a high-speed device which is essential for high-speed system such as optical storage system or mobile communication system, and proposes 0.8${\mu}m$ BiCMOS Process which integrates LDD nMOS, LDD pMOS and SAVEN bipolar transistor into one-chip. The SPICE parameters of LDD nMOS, LDD pMOS and SAVEN Bipolar transistor are extracted, and comparator operating at 500MHz sampling frequency is designed with them. The small Parasitic capacitances of SAVEN bipolar transistor have a direct effect on decreasing recovery time and regeneration time, which is helpful to improve the speed of the comparator. Therefore the SAVEN bipolar transistor with high cutoff frequency is expected to be used in high-speed system.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.26 no.9
• /
• pp.1359-1368
• /
• 1989

In this paper, the composite BiCMOS transistor which combines a bipolar transistor and a MOS transistor in a cascade type, is analyzed in terms of I-V characteristics and small signal equivalent circuit. As a result, it has a larger driving capability than MOS transistor and a more extended rante of input voltage than bipolar transistor. Next, a BiCMOS differential amplifier as its application example is designed and compared with the CMOS one and the bipolar one. It increases the driving capability of the CMOS differential amp and improves the linear operation region of the bipolar differential amp.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.27 no.3
• /
• pp.167-171
• /
• 2014

This paper examines the destruction behavior of NPN BJT (bipolar junction transistor) by repetition pulse. The injected pulse has a rise time of 1 ns and the maximum peak voltage of 2 kV. Pulse was injected into the base of transistor. Transistor was destroyed, current flows even when the base power is turned off. Cause the destruction of the transistor is damaged by heat. Breakdown voltage of the transistor is 975 V at single pulse, and repetition pulse is 525~575 V. Pulse repetition rate increases, the DT (destruction threshold) is reduced. Pulse Repetition rate is high, level of transistor destruction is more serious.

• ETRI Journal
• /
• v.31 no.5
• /
• pp.604-606
• /
• 2009

The primary dose effects on an insulated gate bipolar transistor (IGBT) irradiated with a $^{60}Co$ gamma-ray source are found in both of the components of the threshold shifting due to oxide charge trapping in the MOS and the reduction of current gain in the bipolar transistor. In this letter, the IGBT macro-model incorporating irradiation is implemented, and the electrical characteristics are analyzed by SPICE simulation and experiments. In addition, the collector current characteristics as a function of gate emitter voltage, VGE, are compared with the model considering the radiation damage of different doses under positive biases.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.28A no.10
• /
• pp.821-829
• /
• 1991

In this paper, a BICMOS technology that has CMOS devices for digital application and bipolar devices for high voltage (80V) analog applications is presented. Basic concept to design BICMOS device is simple process technology without making too many performance trade-offs. The base line process is poly gate p-well CMOS process and three additional masking steps are added to improve bipolar characteristics. The key ingredients of bipolar integration are n+ buried layer process, up/down isolation process and p-well base process. The bipolar base region is formed simultaneously with the region of CMOS p-well area to reduce mask and heat cycle steps. As a result, hFE value of NPN bipolar transistor is 100-150(Ic=1mA). Collector resistance value is 138 ohm in case of bent type collector structure. Breakdown voltage of BVebo, BVcbo and BVceo are 21V, 115V and78V respectively. Threshold voltage is ${\pm}$1.0V for NMOS and PMOS transistor. Breakdown voltage of NMOS and PMOS transistor is obtained 22V and 19V respectively. 41 stage CMOS ring oscillator has 0.8ns delay time.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 1992.05a
• /
• pp.61-61
• /
• 1992

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.21 no.1
• /
• pp.23-28
• /
• 2008

In this paper, transient characteristics of the Punch Through Insulated Gate Bipolar Transistor (PT-IGBT) have been studied. On the contrary to Non-Punch Through Insulated Gate Bipolar Transistor(NPT-IGBT), it has a buffer layer and reduces switching power loss. It has a simple drive circuit controlled by the gate voltage of the MOSFET and low on-state resistance of the bipolar junction transistor. The transient characteristics of the PT-IGBT have been analyzed analytically. Excess minority carrier and charge distribution in active base region, the rate of anode voltage with time are expressed analytically by adding the influence of buffer layer. The experimental data is obtained from manufacturer. The theoretical predictions of the analysis have been compared with the experimental data obtained from the measurement of a device(600 V, 15 A) and show good agreement.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.44 no.4
• /
• pp.490-495
• /
• 1995

A bipolar junction transistor which exihibits 1000V breakdown voltage is designed and fabricated using FLR (Field Limiting Rings). Three dimensional effects on the breakdown voltage is investigated in the cylindrical coordinate and the simulation results are compared with the results in the rectangular coordinate. Breakdown voltage of the device with 3 FLR is simulated to be 1420V in the cylindrical coordinate while it is 1580V in rectangular coordinate. Bipolar junction transistor has been fabricated using the epitaxial wafer of which resistivity is 86 .OMEGA.cm and thickness is 105 .mu.m. Si$_{3}$N$_{4}$ and glass are employed for the passivation. Breakdown of the fabricated device is measured to be 1442V which shows better greement with the simulation results in cylindrical coordination.

• Proceedings of the KIEE Conference
• /
• 1993.07b
• /
• pp.777-780
• /
• 1993

An insulated gate bipolar transistor(IGBT) is a MOS gate turn on/off bipolar transistor which combines the attributes of the MOSFET and bipolar transistor. Because of its limitation of power capability compared to thyristor or GTO, some parallel connection of IGBT has been studied to improve the limitation of current capabillity. In this paper, the switching effects from the unbalance of internal parameters of IGBT and the turn-off snubber characteristics are investigated using SPICE program.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2000.07a
• /
• pp.25-28
• /
• 2000

In this study, Transient Characteristics of the Punch-Through Insulated Gate Bipolar Transistor (PT-IGBT) has been studied. On the contraty to Non-Punch Through Insulated Gate Bipolar Transistor(NPT-IGBT), PT-IGBT has buffer layer It has a simple drive circuit controlled by the gate voltage of the MOSFET and the low on-state resistance of the bipolar junction transistor. In this paper, the transient characteristics with temperature of the PT-IGBT has been analyzed analytically. PT-IGBT is made to reduce switching power loss. Excess Minority carrier distribution inactive base region and base charge, the rate of voltage with time is expressed analytically to include buffer layer.