• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.8 s.338
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• pp.11-16
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• 2005

This paper proposes a bit manipulation accelerator (BMA) having application specific instructions, which efficiently supports scrambling, convolutional encoding, puncturing, and interleaving. Conventional DSPs cannot effectively perform bit manipulation functions since かey have multiply accumulate (MAC) oriented data paths and word-based functions. However, the proposed accelerator can efficiently process bit manipulation functions using parallel shift and Exclusive-OR (XOR) operations and bit jnsertion/extraction operations on multiple data. The proposed BMA has been modeled by VHDL and synthesized using the SEC $0.18\mu m$ standard cell library and the gate count of the BMA is only about 1,700 gates. Performance comparisons show that the number of clock cycles can be reduced about $40\%\sim80\%$ for scrambling, convolutional encoding and interleaving compared with existing DSPs.

• Journal of Korea Multimedia Society
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• v.21 no.7
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• pp.764-771
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• 2018

In this paper, we propose a high-quality image acquisition algorithm using only a single image, which the high-quality image is normally referred as HDR ones. In order to acquire the HDR image, conventional methods need many images having different exposure values at the same scene and should delicately adjust the color values for a bit-expansion or an exposure fusion. Thus, they require considerable calculations and complex structures. Therefore, the proposed algorithm suggests a completely new approach using one image for the high-quality image acquisition by applying statistical difference and histogram manipulation, or histogram specification, techniques. The techniques could control the pixel's statistical distribution of the input image into the desired one through the local and the global modifications, respectively. As the result, the quality of the proposed algorithm is better than those of conventional methods implemented in commercial image editing softwares.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6C
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• pp.594-600
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• 2002

A data manipulation unit capable of bit partitioned shift and various multimedia data type conversions in addition to conventional shift, is presented. Utilizing the similarity between the data type conversion and the shift, the addition of small amount of interconnections to conventional barrel shifter enables data type conversion as well as shift operations with minimal hardware overhead. The presented data manipulation unit is composed of the shifter block for conventional shift and a pack and a unpack block. It has been designed with verilog HDL and the VLSI implementation results using compass 0.6 um standard cell are discussed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.1939-1947
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• 1999

This paper proposes new line code BIM (Bit Insertion and Manipulation) that is designed to overcome the problems of existing line codes. The block code, one of typical existing line code, has good transmission performance but difficulty in implementation. The other typical existing line code, bit insertion code, is easy to implementation but has bad transmission performance. BIM code in this paper could provide not only good performance but also provides simplicity in the implementation by combining the good points of block code into it of bit insertion code properly. In this paper, 5B6B type BIM code is designed. Designed 5B6B BIM code shows good transmission performance such $\pm$2 DSV, 0 RSD, 7 maximum run length and also it can be implemented under 2000 gates and need only 1 bit redundancy.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.1
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• pp.64-83
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• 1991

This paper is to design and implement the Korean authoring tool SMAT which is able to generate a high quality instruction software with simple manipulation without a special programming knowledge insurrounding IBM 16/32 bit pc XT/AT.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.226-229
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• 1987

This paper was aimed to, using a new data structure, develop a set of algorithms to execute the output function of Digital System. These functions were represented as directed, acyclic graphs. by applying many restrictions on vertices on graph, the efficient manipulation of boolean function was accomplished. The results were as follows; 1. A canonical representation of a boolean function was created by the reduction algorithm. 2. The operation of two functions was accomplished using t he apply algorithm, according to the binary operator. 3. The arguments having 1 as the value nf function were enumerated using the satisfy algorithm. 4. Composing TTL 74181 4-bit ALU and 74182 look-ahead carry generator, the ALU having 4-bit and 16-bit as word size was implemented.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1965-1966
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• 2008

The manipulation of Boolean functions is a fundamental part of computer science, and many problems in the design and testing of digital systems can be expressed as a sequence of operations. It is mainly a paper of our research on the techniques of Boolean function manipulation using Binary Decision Diagram(BDDs) and their applications for VLSI CAD System. In many practical applications related to digital system design, it is a basic technique to use ternary-valued functions. In this paper, we discuss the methods for representing logical values.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.181-184
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• 2000

In this paper, we described a design of the input buffer system for efficiently dealing with MPEG audio bitstream to demux header and side information, audio data. In order to overcome the limitations of fixed-word manipulation in bitstream demuxing, we proposed a new variable length bit retrieval system with FSM sequencer supporting MPEG audio frame format, and serial buffer demuxing audio stream, FIFO circular buffer including header and side information.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1275-1278
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• 2006

A display panel image data manipulator for SOP or SOG is presented. It is capable of all the shift operations for MPEG decoders, graphic processors and controllers as well as data pack, merging, bit split and reformation operations to improve speed and memory utilization. To alleviate poly-Si low yield, redundancy based fault recovery scheme is introduced utilizing regular structure.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.2806-2808
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• 2005

The Controller Area Network (CAN) is being widely used for real-time control application and small-scale distributed computer controller systems. When the stuff bits are generated by bit-stuffing mechanism in the CAN network, it causes jitter including variations in response time and delay. In order to eliminate this jitter, stuff bit must be controlled to minimize the response time and reduce the variation of data transmission time. At first, this paper shows that conventional CAN protocol causes the transmission time delay. Secondly, this paper proposes the method to reduce the stuff bits by restriction of available identifier. Finally, data manipulation method can be reduced the number of stuff-bits in the data field. The proposed restriction method of ID and manipulating data field are pretty useful to the real-time control strategy with respect to performance. These procedures are implemented in local controllers of the ISHURO (Inha Semyung Humanoid Robot).