• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.397-404
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• 2012

Thermal generation by power dissipation of the highly integrated System on Chip (SoC) device is irregularly distributed on the intra chip. It leads to thermal increment of the each thermally different region and effects on the propagation timing; consequently, the timing violation occurs due to the misestimated number of buffers. In this paper, the timing budgeting methodology considering thermal variation which contains buffer insertion with wire segmentation is proposed. Thermal aware LUT modeling for cell intrinsic delay is also proposed. Simulation results show the reduction of the worst delay after implementing thermal aware buffer insertion using by proposed wire segmentation up to 33% in contrast to the original buffer insertion. The error rates are measured by SPICE simulation results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.2
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• pp.67-75
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• 2004

This paper presents a buffer insertion method for RLC-class interconnect structured as a sin91e line or a tree. First, a closed form expression for the interconnect delay of a CMOS buffer driving single RLC line is represented. This expression has been derived by the n-th power law for deep submicrometer technology and occurs to be within 9 percentage of maximal relative error in accuracy compared with the results of HSPICE simulation for various RLC loads. This paper proposes a closed form expression based on this for the buffer insertion of single RLC lines and the buffer sizing algorithms for RLC tree interconnects to optimize path delays. The proposed buffer insertion algorithms are applied to insert buffers for several interconnect trees with a 0.25${\mu}{\textrm}{m}$ CMOS technology and the results are compared against those of HSPICE.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.455-458
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• 2004

We present an efficient heuristic algorithm to reduce glitch power dissipation in combinational circuits. In this paper, the total number of glitches are reduced by replacing existing gates with functionally equivalent ones and by gate sizing which classified into three types and by buffer insertion which classified into two types. The proposed algorithm combines gate freezing, gate sizing. and buffer insertion into a single optimization process to maximize the glitch reduction. Our experimental results show an average of $67.8\%$ glitch reduction and $32.0\%$ power reduction by simultaneous gate freezing, gate sizing, and buffer insertion.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.81-90
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• 2004

For deep submicron (DSM) very large scale integrated circuits (VLSI), it is well known that interconnects have become the dominant factor in determining the overall circuit performance. Buffer insertion is an effective technique of interconnect optimization. When a net has an excessive propagation delay, one or more buffers can be inserted to reduce the delay. Buffers also reduce the crosstalk between neighboring wires. While many conventional methods insert buffers net by net. we have developed new techniques in which buffer locations are simultaneously optimized for all nets. This is to avoid the difficulties in finding the right ordering of nets for buffer insertion. since several nets may compete for a buffer location. We also study buffer insertion with multiple fan-out nets to optimize critical path delay. Elmore delay model is used for delay calculation and the number of buffers for each net is determined to optimize the delay.

• The KIPS Transactions:PartD
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• v.18D no.4
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• pp.225-236
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• 2011

Various applications of LBS (Location Based Services) are being developed to provide the customized service depending on user's location with progress of wireless communication technology and miniaturization of personalized device. To effectively process an amount of vehicles' location data, LBS requires the techniques such as vehicle observation, data communication, data insertion and search, and user query processing. In this paper, we propose the historical location index, GIP-FB (Group Insertion tree with Flexible Buffer Node) and the flexible buffer node technique to adjust the cost of data insertion and search. the designed GIP+ based index employs the buffer node and the projection storage to cut the cost of insertion and search. Besides, it adjusts the cost of insertion and search by changing the number of line segments of the buffer node with user defined time interval. In the experiment, the buffer node size influences the performance of GIP-FB by changing the number of non-leaf node of the index. the proposed flexible buffer node is used to adjust the performance of the historical location index depending on the applications of LBS.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.2
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• pp.415-424
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• 2014

In this paper, we proposed a practical methodology of HFNS (high fanout net synthesis) to use buffer insertion which has been applied in the fields. First, we proposed consideration to execute HFNS and detail techniques for it. Next we proposed post-process method which is necessary to obtain success of HFNS. The buffer-insertion based method for HFNS is a kind of popular technique, but we targeted a practical and commercial aspect of HHNS.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.11 no.1
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• pp.16-24
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• 1986

The queueing delay and the response time of model of the buffer insertion LAN have been derived and its performance has been analyzed in terms of the throughput rate-response time characteristic. The results show that the response time can be improved by increasing the medium data rate, and that it can be reduced by 0.7 msec by transmitting the acknowledgement signal at the network interface unit(NIU) rather than at the hose, when the channel utilization is approximately 0.8. Also, implementation of the buffer insertion protocol has been studied.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.7
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• pp.684-694
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• 2000

For designing circuits for low power systems, the capacitance is an important factor for the power dissipation. Since the capacitance of a gate is proportional to the area of the gate, we can reduce the total power consumption of a circuit by reducing the total area of gates, where total area is a simple sum of all gate areas in the circuit. To reduce the total area, transistor resizing can be used. While resizing transistors, inserting buffer in the proper position can help reduce the total area. In this paper we propose two methods for concurrent transistor sizing and buffer insertion. One method uses template window simulation and the other uses extrapolation. Experimental results show that concurrent transistor sizing with buffer insertion achieved 10-20% more reduction of the total area than when it was done without buffer insertion and template window simulation is more efficient than extrapolation.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1984.10a
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• pp.7-10
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• 1984

In this paper, the advantages of buffer insertion access method in comparison with other access methods to local area networks are analyzed. Sending and Receiving protocols in a data link layer are designed by a software method, We have derived both qeueing delays and the response time for the performance model that is proposed in this paper, and using the computer simulation, analyzed the performance for the proposed model in terms of the throughput rate- response time characteristrics. Based on the proposed model, the hardware design is implemented.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.73-82
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• 2003

In this paper, a simultaneous buffer insertion and routing method is proposed under the constraints of wire and buffer locations by macro or IP blocks. A new grid graph is proposed to describe the regions in which buffers(or both wires and buffers) are not available. Under this grid we describe a method of constructing a buffeted tree that minimize the maximum source to sink delay. The method is based on the dynamic programming with pruning unnecessary partial solutions. The proposed method improved the slack time of the delay by 19% on the average while using less buffers and similar wire length.