• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.9
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• pp.50-57
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• 2011

Conventional bus system architectures are composed of several components such as master, arbiter, decoder and slave modules. The arbiter plays a role in bus arbitration according to the selected arbitration method, since several masters cannot use the bus concurrently. Typical priority strategies used in high performance arbiters include static priority, round robin, TDMA and lottery. Typical arbitration algorithms always consider the bus priority primarily, while the bus utilization is always ignored. In this paper, we propose an arbitration method using bus utilization for the operating block of each master. We verify the performance compared with the other arbitration methods through the TLM(Transaction Level Model). Based on the performance verification, the conventional fixed priority and round-robin arbitration methods cannot set the bus utilization. Whereas, in the case of the conventional TDMA and lottery arbitration methods, more than 100,000 cycles of bus utilization can be set by the user, exhibiting differences of actual bus utilization up to 50% and 70%, respectively. On the other hand, we confirm that for the proposed arbitration method, the matched bus utilization set by the user was above 99% using approximately 1,000 cycles.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.80-86
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• 2010

The conventional bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in arbitrating the bus. The efficiency of bus usage can be determined by the selection of arbitration method. Fixed Priority, Round-Robin, TDMA and Lottery arbitration policies are studied in the conventional arbitration method where the bus priority is primarily considered. In this paper, we propose the arbitration method that calculates the bus utilization of each master. Furthermore, we verify the performance compared with the other arbitration methods through TLM(Transaction Level Model). From the results of performance verification, the arbitration methods of Fixed Priority and Round-Robin can not set the bus utilization and those of TDMA and Lottery happen the error of 50% and 70% respectively compared with bus utilization set by user in more than 100,000 cycles. On the other hand, the bandwidth-award bus arbitration method remains the error of less than 1% since approximately 1000 cycles, compared with bus utilization set by user.

• International Journal of Highway Engineering
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• v.19 no.2
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• pp.143-152
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• 2017

PURPOSES : This study intends to estimate the tangible benefits derived from the integration of operations of an Express Intercity Bus Terminal and a Highway Service Area. METHODS: For the study, a highway service area was chosen to function as a bus terminal, integrating its services with that of a nearby bus terminal plagued by operating losses. The exercise also helped improve mobility owing to the introduction of local buses between the terminals and utilization of the existing infrastructure such as rest areas. Thus, a terminal that was not being utilized for its intended functionality was integrated with an existing facility to improve the utilization of both and subsequently aid local development. The impact of the exercise was then measured by evaluating the variation in utilization efficiency, operating costs, travel time between two regions (Seoul-Jeomchon and Seoul-Geumsan), and the social costs before and after the integration of the two facilities. RESULTS :The impact of the integration was an increase in utilization efficiency, a decrease in operating cost, a decrease in travel time, and a decrease in social cost in both the regions. The benefits of improved utilization and cost saving can be passed on to the citizens in the form of discounts. A local power generation facility will eventually replace the bus terminal, which can revitalize the local economy. CONCLUSIONS :The integration of the highway service area with the bus terminal is expected to have a win-win effect on the passengers as well as the operators. The study also proposes a sustainable strategic plan for existing terminals and rest areas to implement a method to compete with KTX transportation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.9
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• pp.2078-2082
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• 2010

The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. Conventional arbitration method is considered bus priority primarily, actual bus utilization didn't considered. In this paper, we propose arbitration method using bus utilization operating block of each master, we verify the performance compared with the other arbitration methods through throughput performance. From the result of performance verification, we confirm that proposed arbitration method, matched bus utilization set by the user 40%, 20%, 20%, 20%.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.8
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• pp.1064-1073
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• 1995

On a bus-based shared memory multiprocessing system, the system bus monitoring and analysis are crucial for system integration test and performance analysis. In this paper, the design and implementation of a bus monitoring instrument for the TICOM-III system are decribed. The instrument dedicated to TICOM-III, which is called the Bus Information Procssing Unit, analyzes the bus state and measures the bus utilization. It performs many useful functions to help debugging the system, and offers a simple user interface.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.499-502
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• 1999

This paper presents a PCI (Peripheral Component Interconnect) controller embedded in a multimedia processor, called FLOVA (FLOating point VLIW Architecture), targeting for 3D graphics applications. Fast I/O interfaces are essential for multimedia processors which usually handle large amount of multimedia data. Therefore, in FLOVA, PCI bus is adopted for I/O interface due to fast burst transaction. However, there are several problems in implementation and verification to use burst transaction of PCI. It is difficult to handle data transaction between two units which have two different operating frequency. FLOVA has more higher operating frequency about 100MHz than that of PCI local bus and it makes lower utilization of FLOVA bus. Also, traditional simulation is not sufficient for verification of PCI functionality. In this paper, we propose buffering schemes to implement the PCI controller with wide bandwidth and high bus utilization. Also, this paper shows how to verify the PCI controller using real PCI bus environments before its fabrication.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.32 no.3D
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• pp.213-222
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• 2012

After enforcing 2007 semi-public management system of intra-city bus, Busan city has tried to promote the bus utilization through bus service improvements. As an effort for this, we attempted to clarify the main factors affecting to bus service satisfaction targeting intra-city bus users. In this study, 20 subcategories of intra-city bus service were assorted into 6 factors: Basic Service, Safe Driving, Route Information, Comfort, Cleanliness and Facilities, then the preference for each detailed bus service were analyzed. And the effects for bus service satisfaction were shown under the various conditions according to the general characteristics of intra-city bus users (gender, age), behavioral traffic characteristics (frequency of use, boarding time) and transportation environments (temperature, rainfall). These results would be important basic data for decision-making in bus policy for climate change and establishment of operating plan for bus utilization.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1815-1827
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• 1993

In this paper, we evaluate the performance of a Futurebus based multiprocessor system with MESI cache coherence protocol for four bus transaction types. Graphical symbols and compiler of SLAM II are used in modeling and simulation. A steady-state probability of each state for MESI protocol is computed by a Markov chain. The probability of each state is used as an input value for a correct simulation. Processor utilization, memory utilization, bus utilization, and the waiting time for bus arbitration are measured in terms of the number of processors, the hit ratio of cache memory, the probability of internal operation, and bus bandwidth.

• ETRI Journal
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• v.10 no.3
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• pp.83-91
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• 1988

This paper describes the architecture and the performance analysis of a multiprocessor system, which is based on the shared memory and single system bus. The system bus provides the pended protocol for the multiprocessor environment. Analyzing the processor utilization, address/data bus utilization and memory conflicts, we use a simulation model. The hit ratio of private cache memory is a major factor on the linear increase of the performance of a shared memory based multiprocessor system.

• 제어로봇시스템학회:학술대회논문집
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• 1991.10b
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• pp.1805-1810
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• 1991

This paper derives the upper and the lower bound of the mean cycle time and the mean service time of the class 6 and the class 4, within which the minimum utilization constrain of the class 4 is guaranteed. Also, derived are conditions under which the token bus network is stable or unstable. These bounds and stable conditions are represented in terms of the high priority token hold time, the token rotation time and the arrival rate and the total station number etc. This paper suggest a parameter tuning algorithm in a partially symmetric token bus network with two classes, which maximizes the token rotation time for a suitable high priority token hold time and at the same time meets the stability condition of the network, the real time constraint and the minimum utilization constraint of the class 4.