• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.11a
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• pp.278-281
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• 1999

In this paper, Squential circuit was implemented by decision diagram that can analyze and test large amount of functions easily. First of all, Memery device of multiple valued squential circuit was used D F/F, implemented with CMOS current mode. The opreation property of this circuit involved by PSPICE simulation. The result of Decision Diagram sequential circuit is simple and regular for selecting wire routing and posesses the property of analyze, testing. so it suitable for VLSI implementation.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.5
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• pp.278-286
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• 2000

A new large-scale network geometric analysis is introduced. For a large-scale circuit, it must be analyzed with a geometric diagram and figure. So many equations are induced from a geometric loop-node diagram. The results are arranged into a simple matrix, of course. In case of constructing a network diagram, it is not easy to handle voltage and current sources together. Geometric loop analysis is related to voltage sources, and node analysis is to current sources. The reciprocal transfer is possible only to have series or parallel impedance. If not having this impedance, in order to obtain equivalent circuit, many equations must be derived. In this paper a loop-reduction method is proposed. With this method current source branch is included into the other branch, and disappears in circuit diagram. So the number of independent circuit equations are reduced as much as that of current sources. The number is not (b-n+1), but (b-n+1-p). Where p is the number of current sources. The reduction procedure is verified with a geometric principle and circuit theory. A resultant matrix can be constructed directly from this diagram structure, not deriving circuit equations. We will obtain the last results with the help of a computer.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.124.4-124
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• 2001

It needs a skillful experience to design and implement sequential circuits with a relay circuit or LD (Ladder Diagram). One makes out the operation of relay contacts sequentially in case of analyzing a relay circuit or LD. Still more, the design and analyzing of a complex relay circuit or LD are difficult. In this paper, we propose the EMFG (Extended Mark Graph) representation on relay circuits and LD.

• Journal of Multimedia Information System
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• v.6 no.4
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• pp.323-328
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• 2019

In this paper, a method of constructing an advanced sequential circuit over finite fields is proposed. The method proposed an algorithm for assigning all elements of finite fields to digital code from the properties of finite fields, discussed the operating characteristics of T-gate used to construct sequential digital system of finite fields, and based on this, formed sequential circuit without trajectory. For this purpose, the state transition diagram was allocated to the state dependency code and a whole table was drawn showing the relationship between the status function and the current state and the previous state. The following status functions were derived from the status function and the preceding table, and the T-gate and the device were used to construct the sequential circuit. It was confirmed that the proposed method was able to organize sequential digital systems effectively and systematically.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.108.6-108
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• 2001

The basic circuit block diagram of CMOS current mode sum and subtract circuit is present in this paper. The purpose circuit consists of the invert current circuit and the basic current mirror. The outputs of the circuit are the summing of the both input current [lx+ly] and also the subtract of the both input current [lx+(-ly)]. The SPICE simulation results of the electrical characteristics with level 7 (BSIM3 model version 3.1) MOSFET transistor model of the circuit such as the input dynamic range, the frequency response and some system application have been shown and analyzed.

• Journal of Electrical Engineering and Technology
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• v.10 no.3
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• pp.766-776
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• 2015

It is well known that series arc faults in Low Voltage DC (LVDC) distribution system occur at unintended points of discontinuity within an electrical circuit. These faults can make circuit breakers not respond timely due to low fault current. It, therefore, is needed to detect the series fault for protecting circuits from electrical fires. This paper proposes a novel scheme to detect the series arc fault using Wavelet Singular Value Decomposition (WSVD) and state diagram. In this paper, the fault detector developed is designed by using three criterion factors based on the RMS value of Singular value of Approximation (SA), Sum of the absolute value of Detail (SD), and state diagram. LVDC distribution system including AC/DC and DC/DC converter is modeled to verify the proposed scheme using ElectroMagnetic Transient Program (EMTP) software. EMTP/MODELS is also utilized to implement the series arc model and WSVD. Simulation results according to various conditions clearly show the effectiveness of the proposed scheme.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.52 no.6
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• pp.262-270
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• 2003

In this paper, the characteristics of single-phase line-start permanent magnet synchronous motor driven by constant voltage are analyzed on d-q axis vector diagram and compared with that of current controlled motor. The coupled method of symmetrical coordinates and d-q axis voltage equation are applied to the analysis method like the analysis of single-phase induction motor. From the result of the analysis, it is seen that motors driven by constant voltage source have effects on not only the amplitude of current and torque but also current and current phase angle, so overall characteristics such as power factor and load angle are affected by circuit parameters. For precise analysis and design of single-phase line-start synchronous motor, its characteristics should be analyzed on d-q axis vector plan in consideration of the variation of circuit parameters.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.228-234
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• 2006

This paper describes a systematic process which can generate a complete circuit specification efficiently for a given recursive DSP algorithm based on an optimal multiprocessor scheduler. The process is composed of two states: scheduling and circuit synthesis. The scheduling part accepts a fully specified flow graph(FSFG) as an input, and generates an optimal synchronous multiprocessor schedule. Then the circuit synthesis part translates the modified schedule into a complete circuit diagram including a control specification. The circuit diagram can be applied to a silicon compiler for VLSI layout generation. This paper illustrates the whole process with an example of a second order Gray-Market lattice filter.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.69-72
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• 2003

This paper presents a current-mode multiple-input minimum circuit. The proposed circuit can be implemented by applying De Morgan’s law. The circuit diagram is simple and modular. It operates using a single 2.5V supply and has very low dissipation. The realization method is suitable for fabrication using CMOS technology and all transistors are operated in their saturation region. The performances of this proposed circuit were studied using the PSPICE analog simulation program. The simulation results show the approval of this circuit that it has adequate basic performances for a real-time fuzzy controller and a fuzzy computer.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.1-12
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• 1999

A new algorithm of constructing binary decision diagram(BDD) for design verification of switch-level circuits is proposed in this paper. In the switch-level circuit, functions are characterized by serial and parallel connections of switches and the final logic values may have high-impedance and unstable states in addition to the logic values of 0 and 1. We extend the BDD to represent functions of switch-level circuits as acyclic graphs so called switch-level binary decision diagram (SLBDD). The function representation of the graph is in the worst case, exponential to the number of inputs. Thus, the ordering of decision variables plays a major role in graph sizes. Under the existence of pass-transistors and domino-logic of precharging circuitry, we also propose an input ordering algorithm for the efficiency in graph sizes. We conducted several experiments on various benchmark circuits and the results show that our algorithm is efficient enough to apply to functional simulation, power estimation, and fault-simulation of switch-level design.