• Korean Journal of Materials Research
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• v.13 no.11
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• pp.711-716
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• 2003

Gate length, height, and silicide thickness have all been shrinking linearly as device density has progressively increased over the years. We investigated the effect of the cobalt diffusion during the silicide formation process on the 60$\AA$-thick gate oxide lying underneath the Ti/Co and Co/Ti bilayers. We prepared four different cobalt silicides, which have similar sheet resistance, made from the film structure of Co/Ti(interlayer), and Ti(capping layer)/Co, and peformed the current-voltage, time-to-break down, and capacitance-voltage measurements. Our result revealed that the cobalt silicide process without the Ti capping layer allowed cobalt atoms to diffuse into the upper interface of gate oxides. We propose that 100$\AA$-thick titanium interlayer may lessen the diffusion of cobalt to gate oxides in 1500-$\AA$ height polysilicon gates.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.1-9
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• 2003

In this paper, a novel Ni silicide technology with Cobalt interlayer and Titanium Nitride(TiN) capping layer for sub 100 nm CMOS technologies is presented, and the device parameters are characterized. The thermal stability of hi silicide is improved a lot by applying co-interlayer at Ni/Si interface. TiN capping layer is also applied to prevent the abnormal oxidation of NiSi and to provide a smooth silicidc interface. The proposed NiSi structure showed almost same electrical properties such as little variation of sheet resistance, leakage current and drive current even after the post silicidation furnace annealing at $700^{\circ}C$ for 30 min. Therefore, it is confirmed that high thermal robust Ni silicide for the nano CMOS device is achieved by newly proposed Co/Ni/TiN structure.

• Korean Journal of Metals and Materials
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• v.46 no.2
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• pp.88-96
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• 2008

Thermal evaporated 10 nm-$Ni_{50}Co_{50}$/(70 nm-poly)Si films were deposited to examine the energy saving properties of silicides formed by rapid thermal annealing at temperature ranging from 500 to $1,100^{\circ}C$ for 40 seconds. Thermal evaporated 10 nm-Ni/(70 nm-poly)Si films were also deposited as a reference using the same method for depositing the 10 nm-$Ni_{50}Co_{50}$/(70 nm-poly)Si films. A four-point probe was used to examine the sheet resistance. Transmission electron microscopy (TEM) and X-ray diffraction XRD were used to determine cross sectional microstructure and phase changes, respectively. UV-VIS-NIR and FT-IR (Fourier transform infrared spectroscopy) were used to examine the near-infrared (NIR) and middle-infrared (MIR) absorbance. TEM analysis confirmed that the uniform nickel-cobalt composite silicide layers approximately 21 to 55 nm in thickness had formed on the single and polycrystalline silicon substrates as well as on the 25 to 100 nm thick nickel silicide layers. In particular, nickel-cobalt composite silicides showed a low sheet resistance, even after rapid annealing at $1,100^{\circ}C$. Nickel-cobalt composite silicide and nickel silicide films on the single silicon substrates showed similar absorbance in the near-IR region, while those on the polycrystalline silicon substrates showed excellent absorbance until the 1,750 nm region. Silicides on polycrystalline substrates showed high absorbance in the middle IR region. Nickel-cobalt composite silicides on the poly-Si substrates annealed at $1,000^{\circ}C$ superior IR absorption on both NIR and MIR region. These results suggest that the newly proposed $Ni_{50}Co_{50}$ composite silicides may be suitable for applications of IR absorption coatings.

• Journal of the Korean Ceramic Society
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• v.38 no.10
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• pp.871-875
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• 2001

Cobalt silicidation at sidewall spacer edge of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) with post annealing treatment for capacitor forming process has been investigated as a function of dopant species. Cobalt silicidation of nMOSFET with n-type Lightly Doped Drain (LDD) and pMOSFET with p-type LDD produces a well-developed cobalt silicide with its lateral growth underneath the sidewall spacer. In case of pMOSFET with n-type LDD, however, a void is formed at the sidewall spacer edge with no lateral growth of cobalt silicide. The void formation seems to be due to a retarded silicidation process at the LDD region during the first Rapid Thermal Annealing (RTA) for the reaction of Co with Si, resulting in cobalt mono silicide at the LDD region. The subsequent second RTA converts the cobalt monosilicide into cobalt disilicide with the consumption of Si atoms from the Si substrate, producing the void at the sidewall spacer edge in the Si region. The void formed at the sidewall spacer edge serves as a resistance in the current-voltage characteristics of the pMOSFET device.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.387-390
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• 1988

The increases in the packing density and the resulting shrinkage of silicon integrated circuit dimensions led to the investigation and successful of the deposited silicide layers as the gate and interconnection and contact metallization. In this paper evaporated Co films on n-Si have been rapid thermal annealed in $N_2$ambient at temperature of $400^{\circ}C-1000^{\circ}C$. The Co silicide formation is characterized by sheet resistance (4PP). Also, silicide growth rate and its reproductivity has been examined by SEM.

• Journal of Information Display
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• v.1 no.1
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• pp.63-69
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• 2000

In order to improve both the level and the stability of electron emission, Mo and Co silicides were formed from Mo mono-layer and Ti/Co bi-layers on single crystal silicon field emitter arrays (FEAs), respectively. Using the slope of Fowler-Nordheim curve and tip radius measured from scanning electron microscopy (SEM), the effective work function of Mo and Co silicide FEAs were calculated to be 3.13 eV and 2.56 eV, respectively. Compared with silicon field emitters, Mo and Co silicide exhibited 10 and 34 times higher maximum emission current, 10 V and 46 V higher device failure voltage, and 6.1 and 4.8 times lower current fluctuation, respectively. Moreover, the emission currents of the silicide FEAs depending on vacuum level were almost the same in the range of $10^{-9}{\sim}10^{-6}$ torr. This result shows that silicide is robust in terms of anode current degradation due to the absorption of air molecules.

• Korean Journal of Materials Research
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• v.16 no.10
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• pp.656-662
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• 2006

We fabricated thermal evaporated 10 nm-$Ni_xCo_{1-x}$ (x=0.2, 0.5 and 0.8) /(poly)Si films to form nanothick cobalt nickel composite silicides by a rapid thermal annealing at $700{\sim}1100^{\circ}C$ for 40 seconds. A field emission scanning electron microscope and a micro-Raman spectrometer were employed for microstructure and silicon residual stress characterization, respectively. We observed self-aligned micro-pinholes on single crystal silicon substrates silicidized at $1100^{\circ}C$. Raman silicon peak shift indicates that the residual tensile strain of $10^{-3}$ in single crystal silicon substrates existed after the silicide process. We propose thermal stress from silicide exothermic reaction and high temperature silicidation annealing may cause the pinholes. Those pinholes are expected to be avoided by lowering the silicidation temperature. Our results imply that we may use our newly proposed composite silicides to induce the appropriate strained layer in silicion substrates.

• Journal of the Korean Ceramic Society
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• v.38 no.9
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• pp.782-786
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• 2001

Cobalt silicide has been employed to Embedded DRAM (Dynamic Random Access Memory) and Logic (EDL) as contact material to improve its speed. We have investigated the influences of Ti and TiN capping layers on cobalt-silicided Complementary Metal-Oxide-Semiconductor (CMOS) device characteristics. TiN capping layer is shown to be superior to Ti capping layer with respect to high thermal stability and the current driving capability of pMOSFETs. Secondary Ion Mass Spectrometry (SIMS) showed that the Ti capping layer could not prevent the out-diffusion of boron dopants. The resulting operating current of MOS devices with Ti capping layer was degraded by more than 10%, compared with those with TiN.

• Korean Journal of Materials Research
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• v.17 no.2
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• pp.73-80
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• 2007

For the sub-65 nm CMOS process, it is necessary to develop a new silicide material and an accompanying process that allows the silicide to maintain a low sheet resistance and to have an enhanced thermal stability, thus providing for a wider process window. In this study, we have evaluated the property and unit process compatibility of newly proposed composite silicides. We fabricated composite silicide layers on single crystal silicon from $10nm-Ni_{1-x}Co_x/single-crystalline-Si(100),\;10nm-Ni_{1-x}Co_x/poly-crystalline-\;Si(100)$ wafers (x=0.2, 0.5, and 0.8) with the purpose of mimicking the silicides on source and drain actives and gates. Both the film structures were prepared by thermal evaporation and silicidized by rapid thermal annealing (RTA) from $700^{\circ}C\;to\;1100^{\circ}C$ for 40 seconds. The sheet resistance, cross-sectional microstructure, surface composition, were investigated using a four-point probe, a field emission scanning probe microscope, a field ion beam, an X-ray diffractometer, and an Auger electron depth profi1ing spectroscopy, respectively. Finally, our newly proposed composite silicides had a stable resistance up to $1100^{\circ}C$ and maintained it below $20{\Omega}/Sg$., while the conventional NiSi was limited to $700^{\circ}C$. All our results imply that the composite silicide made from NiCo alloy films may be a possible candidate for 65 nm-CMOS devices.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.6 no.3
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• pp.270-272
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• 2005

The behavior of surface oxidation on cobalt silicide layer was investigated under rapid thermal oxidation (RTO) conditions. The cobalt silicide layer was prepared on p-type silicon substrates. We used Ti thin film as a capping layer in order to measure the degree of oxidation of the layer. Oxide grew faster on the cobalt silicide prepared with the Ti capping layer to reach ca $500{\AA}$ at $700^{\circ}C$ in thickness. The oxide film kept growing under $550^{\circ}C\~700^{\circ}C$ of the RTO condition, resulting in a saturated state above $500{\AA}$.