• 한국정보통신학회논문지
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• 제19권12호
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• pp.2892-2898
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• 2015

양극성 이중 독립 게이트 실리콘 나노와이어 전계 효과 트랜지스터를 새롭게 제안한다. 제안한 트랜지스터는 극성 게이트와 제어 게이트를 가지고 있다. 극성게이트의 바이어스에 따라서 N형과 P형 트랜지스터의 동작을 결정할 수 있고 제어 게이트의 전압에 따라 트랜지스터의 전류 특성을 제어할 수 있다. 2차원 소자 시뮬레이터를 이용해서 양극성 전류-전압 특성이 동작하도록 두 개의 게이트들과 소스 및 드레인의 일함수를 조사했다. 극성게이트 4.75 eV, 제어게이트 4.5 eV, 소스 및 드레인 4.8 eV일 때 명확한 양극성 특성을 보였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2000년도 전력전자학술대회 논문집
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• pp.137-140
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• 2000

This paper proposes an improved soft switching two-transistor forward converter which uses a novel lossless snubber circuit to effectively control the turn-off dv/dt rate of the main transistors. In the proposed soft switching implementation the turn-off voltage traces across the main two transistors are almost the same contributing to reduce the total capacitive turn-on loss and the snubber current is divided into the two transistors resulting in distributed thermal stresses

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2016년도 추계학술대회
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• pp.170-171
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• 2016

A surface potential model is introduced for L-shaped tunnel field-effect-transistor(L-TFET). Excellent agreement is obtained when model results are compared with TCAD data.

• Bulletin of the Korean Chemical Society
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• 제35권3호
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• pp.731-736
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• 2014

An organic junction transistor with a vertical structure based on an active layer of poly(3-hexylthiophene) was fabricated by facile micro-contact printing combined with the Langmuir-Schaefer technique, without conventional e-beam or photo-lithography. Direct printing and subsequent annealing of Au-nanoparticles provided control over the thickness of the Au electrode and hence control of the electrical contact between the Au electrode and the active layer, ohmic or Schottky. The junction showed similar current-voltage characteristics to an NPN-type transistor. Current through the emitter was simply controllable by the base voltage and a high transconductance of ~0.2 mS was obtained. This novel fabrication method can be applied to amplifying or fast switching organic devices.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.167-168
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• 2007

Design Rule이 작아짐에 따라 Transistor performance 향상을 위한 여러 방안중 SEG 공정이 적용되고 있으며 이에 따른 Transistor 특성 연구 결과이다. SEG공정 적용시 SEG Profile에 따라 Transistor의 Short Channel Effect 열화가 발생하였고 그 원인은 Sidewall Facet발생으로 추정되며 이를 개선시 Tr 특성이 개선됨을 확인하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.166-170
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• 2003

This paper presents the TTFC(Two Transistor Forward Converter) using Synchronous Rectifier of Compulsory Control-driver. The two transistor forward circuit is used to decrease voltage stress of primary side and the synchronous rectifier is used to reduce current stress of secondary side. Previous synchronous rectifier's MOSFET of TTFC have long dead time This paper presents synchronous rectifier of compulsory control-driver for minimized dead time. This paper compared with diode rectifier, self-driven synchronous rectifier and compulsory control-driver synchronous rectifier of TTFC. The principle of operation, feature and design considerations are illustrated and verified through the experiment with a 200W 100kHz MOSFET based experimental circuit.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.156-161
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• 2017

This work presents a novel structure for junction-less tunneling field effect transistor (JL-TFET) with a floating gate over the source region. Introduction of floating gate instead of fixed metal gate removes the limitation of fabrication process suitability. The proposed device is based on a heavily n-type-doped Si-channel junction-less field effect transistor (JLFET). A floating gate over source region and a control-gate with optimized metal work-function over channel region is used to make device work like a tunnel field effect transistor (TFET). The proposed device has exhibited excellent ID-VGS characteristics, ION/IOFF ratio, a point subthreshold slope (SS), and average SS for optimized device parameters. Electron charge stored in floating gate, isolation oxide layer and body doping concentration are optimized. The proposed JL-TFET can be a promising candidate for switching performances.

• 한국전기전자재료학회논문지
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• 제16권10호
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• pp.931-937
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• 2003

The principle of the superconducting vortex flow transistor (SVFT) is based on control of the Abrikosov vortex flowing along a channel. The induced voltage is controlled by a bias current and a control current, instead of external magnetic field. The device is composed of parallel weak links with a nearby current control line. We explained the process to get an I-V characteristic equation and described the method to induce the external and internal magnetic field by the Biot-Savarts law in this paper. The equation can be used to predict the I-V curves for fabricated device. From the equation we demonstrated that the current-voltage characteristics were changed with input parameters. I-V characteristics were simulated to analyze a SVFT with multi-channel by a computer program.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2013년도 춘계학술대회 논문집
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• pp.173-174
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• 2013

• 한국정보전자통신기술학회논문지
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• 제9권1호
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• pp.120-131
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• 2016

본 논문에서는 back-gate bias 전압인 VNN (Negative Voltage)을 이용하여 5V의 MV (Medium Voltage) 소자만 이용하여 FN (Fowler-Nordheim) tunneling 방식으로 write하는 MTP cell을 사용하여 512비트 MTP IP를 설계하였다. 사용된 MTP cell은 CG(Control Gate) capacitor, TG(Tunnel Gate) transistor와 select transistor로 구성되어 있다. MTP cell size를 줄이기 위해 TG transistor와 select transistor를 위한 PW(P-Well)과 CG capacitor를 위한 PW 2개만 사용하였으며, DNW(Deep N-Well)은 512bit MTP cell array에 하나만 사용하였다. 512비트 MTP IP 설계에서는 BGR을 이용한 voltage regulator에 의해 regulation된 V1V (=1V)의 전압을 이용하여 VPP와 VNN level detector를 설계하므로 PVT variation에 둔감한 ${\pm}8V$의 pumping 전압을 공급할 수 있는 VPP와 VNN 발생회로를 제안하였다.