• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.6
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• pp.1537-1544
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• 2012

In this paper, a new integration of linear mapping capability with 4-20mA current loop receiver. This module allow user to change instrument variable instantly. Configurations are easy to set by using console command through serial communication port. Break in current loop or faulty current transmitter are easily detect through indicator. The implementation of the module and the test results are discussed.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.3
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• pp.238-242
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• 1988

It is analyzed how performance of phase-locked loop driven by photodetector current in optical receiver will be changed under the condition that Gaussian thermal noise, pattern noise and shot noise are present and the loop has the nonzero detuning frequency. The phase error variance cahnges with the circuit configuration and the produced noise models. The analyzed results are applied to the previously implemented 90.194Mbps optic system whose loop filter is the improved active noninverting 1-st order lag-lead type.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.233-236
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• 2000

A portable equipment that measures a current and voltage waveform of power transmission lines is pro-posed. In the equipment, the current and voltage, respectively, are detected by a loop coil and a capacitor clamped around the power lines. The detected data is transmitted by an FM wave to the receiver on the ground station. Since the receiver is isolated from the power lines, we do not require high potential insulators for the measurement of current and voltage. The proposed equipment is therefore, small-sized, light, and low in the cost of production. Experimental results presented here show that the equipment can monitor the current flowing in single wire over a ground plane and the potential of the wire.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.67-73
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• 2015

This paper presents a fully integrated 3 - 5 GHz IR-UWB(impulse radio ultra-wide band) RFIC for Location based system. The receiver architecture adopts the energy detection method and for high speed sampling, the equivalent time sampling technique using the integrated DLL(delay locked loop) and 4 bit ADC. The digitally synthesized UWB impulse generator with low power consumption is also designed. The designed IR-UWB RFIC is implemented on $0.18{\mu}m$ CMOS technology. The receiver's sensitivity is -85.7 dBm and the current consumption of receiver and transmitter is 32 mA and 25.5 mA respectively at 1.8 V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.100-105
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• 2010

In this paper, a FM radio receiver integrated circuit has been developed based on $0.5{\mu}m$ CMOS process for Zero-Crossing FM demodulator over the 88MHz to 108MHz band. The receiver is designed with the low-IF architecture, and includes Low Noise Amplifier(LNA), Down-Conversion Mixer, Phase Locked Loop(PLL), IF LPF, and a comparator. The measured results of the LNA and Mixer show that the conversion gain of 23.2 dB, the input PldB of -14 dBm, and the noise figure of 15 dB. The measured analog block of the LPF and comparator show the voltage gain of over 89 dB, and the IF LPF can configure the passband from 600KHz to 1.3MHz with 100KHz step through the internal control register banks. The designed FM radio receiver operates at 4.5V with the total current consumption of 15.3mA, so the total power consumption is about 68.85mW. The commercial FM radio has been successfully received.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.283-286
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• 2003

In this paper, we represent an implementation of burst QPSK receiver for underwater acoustic communication. Transmitter sends 5,000 symbols at 25kHz frequency with 200 kHz D/A sampling rate. The received signal is sampled at 100 kHz. Implemented receiver acquires the frame synchronization, coarse symbol timing estimate, and coarse phase offset estimate using 32 symbol length preamble. The estimated phase offset is used to initiate of 2nd order PLL. The transmission experiment results show that PLL is a mandatory to compensate Doppler shift due to the variation of tidal current.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.153-159
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• 2009

A CMOS frequency synthesizer for $5{\sim}6$ GHz UNII-band sub-harmonic direct-conversion receiver has been developed. For quadrature down-conversion with sub-harmonic mixing, octa-phase local oscillator (LO) signals are generated by an integer-N type phase-locked loop (PLL) frequency synthesizer. The complex timing issue of feedback divider of the PLL with large division ratio is solved by using multimodulus prescaler. Phase noise of the local oscillator signal is improved by employing the ring-type LC-tank oscillator and switching its tail current source. Implemented in a $0.18{\mu}m$ CMOS technology, the phase noise of the LO signal is lower than -80 dBc/Hz and -113 dBc/Hz at 100 kHz and 1MHz offset, respect-tively. The measured reference spur is lower than -70 dBc and the power consumption is 40 m W from a 1.8 V supply voltage.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.6
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• pp.410-415
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• 2014

This paper presents a new rectifier with a bootstrapping technique to reduce the effective drop voltage. An all-digital delay locked loop (ADDLL) circuit was also applied to prevent the reverse leakage current. The proposed rectifier uses NMOS diode connected instead of PMOS to reduce the design size and improve the frequency respond. All the sub-circuits of ADDLL were designed with low power consumption to reduce the total power of the rectifier. The rectifier was implemented in CMOS $0.35{\mu}m$ technology. The peak power conversion efficiency was 76 % at an input frequency of 6.78MHz and a power level of 5W.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.23-29
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• 2011

A dB-linearity improved variable gain amplifier (VGA) for GPS receiver is presented. The Proposed dB-linear current generator has improved dB-linearity error of ${\pm}0.15$dB. The VGA for GPS is designed using proposed dB-linear current generator and composed of 3 stage amplifiers. The IF frequency is assumed as 4MHz and the linearity requirement of the VGA for GPS receiver is defined as 24dBm of IIP3 using cascaded IIP3 equation and the VGA satisfies 24dBm when minimum gain mode. The DC-offset voltage is eliminated using DC-offset cancelation loop. The gain range is from -8dB to 52dB and the dB-linearity error satisfies ${\pm}0.2$dB. The 3-dB frequency has range of 35MHz~106MHz for the gain range. The VGA is designed using 0.18${\mu}m$ CMOS process. The power consumption is 3mW with 1.8V supply voltage.

• ETRI Journal
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• v.29 no.4
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• pp.421-429
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• 2007

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.