• 전자공학회논문지 IE
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• v.45 no.2
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• pp.1-5
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• 2008

In this work, RF performance degradation due to hot carrier effects in SOI MOSFET have been measured and analyzed. The LNA that designed at $V_{GS}=0.8V$, f=2.5GHz, gain is 16.51dB and noise figure is 1.195dB. After stress at SOI, the LNA's gain and noise figure change of 15.3dB and 1.44dB with before stress.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.10
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• pp.2045-2051
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• 2009

A 5-GHz band Low Noise Amplifier(LNA) using SOI MOSFET is designed. To improve the noise performance, depletion-type SOI MOSFET is adopted, and it is designed by the two-stage topology consisting of common-source and common-gate stages for low-voltage operation. The fabricated LNA achieved an S11 of less than -10dB, voltage gain of 21dB with a power consumption of 8.3mW at 5.5GHz, and a noise figure of 1.7dB indicated that the depletion-type LNA improved the noise figure by 0.3dB compared with conventional type. These results show the feasibility of a CMOS LNA employing depletion-type SOI MOSFET for low-noise application.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.41-47
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• 1998

We propose a new high speed and low power SOI inverter with dynamic threshold voltage that can operate with efficient body-bias control and free supply voltage. The performance of the proposed circuit is evaluated by both the BSIM3SOI circuit simulator and the ATLAS device simulator, and then compared with other reported SOI circuits. The proposed circuit is shown to have excellent characteristics. At the supply voltage of 1.5V, the proposed circuit operates 27% faster than the conventional SOI circuit with the same power dissipation.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.48-52
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• 1998

We fabricated the newly proposed nano structure memory with SOI edge channel and a nano dot. The width of the edge channel of this device, which uses the side wall as a channel and has a nano dot on this channel region, was determined by the thickness of the recessed top-silicon layer of SOI wafer. The size of side-wall nano dot was determined by the RIE etch and E-Beam lithography. The I$_{d}$-V$_{d}$, I$_{d}$-V$_{g}$ characteristics of the devices without nano dots and memory characteristics of the devices with nano dots were obtained, where the voltage scan was done between -20 V and 14 V and the threshold voltage shift was about 1 V.t 1 V.

• ETRI Journal
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• v.26 no.6
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• pp.575-582
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• 2004

Fully-depleted silicon-on-insulator (FD-SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the single- raised (SR) and double-raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self-heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self-heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a $1.1\;{\mu}m^2$ 6T-SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra-thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.

• Journal of Multimedia Information System
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• v.5 no.1
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• pp.35-42
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• 2018

Direct volume rendering (DVR) is an important 3D visualization method for medical images as it depicts the full volumetric data. However, because DVR renders the whole volume, regions of interests (ROIs) such as a tumor that are embedded within the volume maybe occluded from view. Thus, conventional 2D cross-sectional views are still widely used, while the advantages of the DVR are often neglected. In this study, we propose a new visualization algorithm where we augment the 2D slice of interest (SOI) from an image volume with volumetric information derived from the DVR of the same volume. Our occlusion-based DVR augmentation for SOI (ODAS) uses the occlusion information derived from the voxels in front of the SOI to calculate a depth parameter that controls the amount of DVR visibility which is used to provide 3D spatial cues while not impairing the visibility of the SOI. We outline the capabilities of our ODAS and through a variety of computer tomography (CT) medical image examples, compare it to a conventional fusion of the SOI and the clipped DVR.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.6
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• pp.28-36
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• 1998

We have proposed a new non-inverting SOI buffer circuit for the high speed operation at low supply voltage. The body biases of main MOS devices in the proposed circuit are controlled dynamically via subsidiary MOS device connected efficiently to the body terminal. We showed current derivability of the body controlled devices obtained by device simulation and compared with that of conventional SOI devices. Delay time characteristics of the buffer circuit were analyzed by SPICE simulation and compared with those of conventional SOI CMOS buffer circuits. Delay time reduction of the SOI buffer over conventional SOI CMOS buffer with same area is about 36 % at $V_{S}$=1.2 V and $C_{L}$=2 pF. pF.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.51-56
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• 2004

We propose and fabricate an 1${\times}$2 asymmetric optical switch by TOE using SOI wafer based on silicon which has very large TOE figure and it is a good material for optical devices. SOI wafer consists of 3 layers; upper Si layer for device(waveguide;core, n=3.5), buried oxide layer for insulator(clad, n=1.5) and Si substrate layer. We designed 1${\times}$2 asymmetric y-branched single mode optical waveguide switch by BPM simulation and metal heater by heat transfer simulation. Fabricated switch shows about 3.5 watts of power consumption and over 20dB of crosstalk between output channels.

• Proceedings of the Optical Society of Korea Conference
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• 2007.07a
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• pp.319-320
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• 2007

We report on the fabrication of two-dimensional Silicon On Insulator (SOI) photonic crystal (PhC) superprism. To optimize the design of 2-D SOI PhC superprism, the photonic band structures (TE-polarization) for triangular lattices and the dispersion surfaces were calculated and analyzed by the plane wave expansion method. Dense 2-D SOI PhC superprism nanostructures with taper input and output waveguide microstructures were successfully fabricated by nanoimprint lithography, followed by inductively coupled plasma (ICP) etching.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.05a
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• pp.145-146
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• 1994

A SOI technology is promising for micromachining: high temperature operation, the fabrication easiness of sophisticated and 3D microstructures, radiation hardness, integrated sensors etc. This paper describes reviews of SOI technologies, and their applications microsensors and microactuators