• Journal of IKEEE
• /
• v.7 no.2 s.13
• /
• pp.188-196
• /
• 2003

In this paper, a demultiplexer for MPEG-2 Transport Stream which can be applied to terrestrial digital broadcast is developed. The demultiplexer separates video, audio, and data from MPEG-2 multimedia stream and transports them to each decoders respectively. While most existing demultiplexers of MPEG-2 transport stream have been developed as hardware systems, but the fast increment of computer's performance enables a software demultiplexer to be worked in realtime. The developed demultiplexer is implemented as a software module called a filter using DirectShow of Microsoft which is based on COM(Component Object Model)and works on the Windows system. The operation of the demultiplexer is verified by using the GraphEdit tool and rendering a test file formatted as MPEG-2 transport stream.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.5
• /
• pp.58-64
• /
• 2008

A 6Gbps 1:2 demultiplexer(DEMUX) IC using $0.18{\mu}m$ CMOS was designed and fabricated. For high speed performance current mode logic(CML) flipflop was used and inductive peaking technology was used so as to obtain higher speed than conventional Current mode logic flipflop. On-chip spiral inductor was designed to maximize the inductive peaking effect using stack structure. Total twelve inductors of $100{\mu}m^2$ area increase was used. The measurement was processed on wafer and 1:2 demultiplexer with and without micro stacked spiral inductors were compared. For 6Gbps data rate measurement, eye width was improved 7.27% and Jitter was improved 43% respectively. Power consumption was 76.8mW and eye height was 180mV at 6 Gbps

• Proceedings of the Optical Society of Korea Conference
• /
• 2003.07a
• /
• pp.262-263
• /
• 2003

In this paper, Gaussian apodized volume grating for demultiplexer is implemented. A 22-channel demultiplexer based on that grating is optically demonstrated. The channel spacing, the interchannel cross-talk level and the channel uniformity of 0.8 nm, -30 dB and 1.5 dB, respectively, are obtained.(omitted)

• Proceedings of the KIEE Conference
• /
• 2005.05a
• /
• pp.148-151
• /
• 2005

This paper proposes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that convert redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was designed using a 0.35${\mu}m$ standard CMOS Process. Proposed demultiplexer is achieved an operating speed of 3Gb/s with a supply voltage of 3.3V and with power consumption of 48mW. Designed circuit is limited by maximum operating frequency of process. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 3Gb/s in submicron process of high of operating frequency.

• The KIPS Transactions:PartA
• /
• v.15A no.3
• /
• pp.135-140
• /
• 2008

This paper describes a high-speed CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with TSMC $0.18{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation. The demultiplexer is achieved the maximum data rate of 20 Gb/s and the average power consumption of 95.85 mW.

• Journal of the Institute of Convergence Signal Processing
• /
• v.8 no.2
• /
• pp.84-90
• /
• 2007

In this paper, the demonstration of a 130-channel optical demultiplexer based on the cascaded volume holographic gratings is presented. By serially adding the second holographic grating, which has different grating period, slant angle, and center wavelength compared to those of the first grating, the operating wavelength range of the optical demultiplexer could be expanded, and therefore, the number of channels of the holographic demultiplexer is increased by twice. As a result of the experiment, a 0.4-nm-spaced demultiplexer with the channel uniformity of 3.5 dB, the 3dB-bandwidth of 0.12nm, and the channel crosstalk of -20dB is experimentally achieved.

• Proceedings of the Optical Society of Korea Conference
• /
• 1990.02a
• /
• pp.227-231
• /
• 1990

A SiO2/Si concave diffraction grating(period: 1.3${\mu}{\textrm}{m}$) for the angular dispersive element of WDM was fabricated by sandwiching the SiO2/Si plane diffraction grating between a slab waveguide and a cylindrical concave block. Using this concave grating and input/output fiber, and wavelength division demultiplexer was composed. The demultiplexer has five channels, the insertion loss of 30dB, the wavelength spacing per channel of 7nm and crosstalk of-15dB.

• Journal of Communications and Networks
• /
• v.12 no.6
• /
• pp.529-532
• /
• 2010

Multi-carrier demultiplexer/demodulator (MCDD) in an on-board processing (OBP) satellite used for digital multimedia services has two typical architectures according to the channel demultiplexing procedure: Multistage multi-carrier demultiplexer (M-MCD) or poly-phase fast Fourier transform (PPF). During the channel demultiplexing, phase and quantization errors influence the performance of MCDD; those errors affect the bit error rate (BER) performance of M-MCD and PPF differently. In this paper, we derive the phase error variances that satisfy the condition that M-MCD and PPF have the same signal to noise ratio according to quantization bits, and then, with these results, analyze the BER performances of M-MCD and PPF. The results provided here may be a useful reference for the selection of M-MCD or PPF in designing the MCDD in an OBP satellite communications system.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.2
• /
• pp.121-126
• /
• 2007

This paper describes a 9.09 Gb/s CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with Samsung $0.35{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the post layout simulation. The demultiplexer is achieved the maximum data rate of 9.09 Gb/s and the average power consumption of 69.93 mW. This circuit is expected to operate at higher speed than 9.09 Gb/s in the deep-submicron process of the high operating frequency.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.10 no.6
• /
• pp.17-22
• /
• 2010

In this paper, integral TS(Transport Stream) demultiplexer of a multi-modal receiver is proposed according to the multiple standards of European terrestrial digital broadcasting DVB-T(Digital Video Broadcasting Terrestrial), and mobile terrestrial digital broadcasting T-DMB(Terrestrial Digital Multimedia Broadcasting). This USB based integral receiver could recover the multi-modal broadcasting audios by memory sharing technique which was utilized to decrease the load by the control of streaming multi-modal broadcasting. As a result of performance analysis for a proposed integral TS demultiplexer, the CPU occupational efficiency of windows based integral demulitiplexing is improved compared with DVB-T, and T-DMB respectively.