• Journal of Digital Convergence
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• v.13 no.7
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• pp.177-182
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• 2015

In a MPC(Multi-Pulse Coding) using excitation source of voiced and unvoiced, it would be a distortion of voice waveform. This is caused by normalization of synthesis speech waveform of voiced in the process of restoration. To solve this problem, this paper present APC-MPC of amplitude-position compensation in a multi-pulses each pitch interval in order to reduce distortion of synthesis waveform. Also, I was implemented that the APC-MPC in coding system. And I evaluate the SNRseg of APC-MPC in 8kbps coding condition of convergence system. As a result, SNRseg of APC-MPC was 13.9dB for female voice and 14.3dB for male voice respectively. And so, I expect to be able to this method for cellular phone and smart phone using excitation source of low bit rate.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.7A
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• pp.735-740
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• 2004

When optical signal power of ONU differs from each other the requirements of an OLT receiver becomes strict and the stable operation of a total PON system can't be obtained. To solve this problem each ONU channel's signal power is measured at the OLT side and control signals to equalize them are generated and sent to each ONU. The proposed scheme is tested after implementation A digital APC circuit is proposed and tested so that it can start or stop LD operation without delay. It helps other ONU to transmit signals without interference and to reduce consuming power.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.7
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• pp.1347-1353
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• 2015

We implemented a 10 Gb/s 4-channel vertical cavity surface emission lasers (VCSEL) driver array in a $0.13{\mu}m$ CMOS process technology. To enhance high current resolution, power dissipation, and chip space area, digital APC/AMC with time division sensing technology is primarily adopted. The measured -3 dB frequency bandwidth is 9.2 GHz; the small signal gain is 10.5 dB; the current resolution is 0.01 mA/step, suitable for the wavelength operation up to 10 Gb/s over a wide temperature range. The proposed APC and AMC demonstrate 5 to 20 mA of bias current control and 5 to 20 mA of modulation current control. The whole chip consumes 371 mW of low power under the maximum modulation and bias currents. The active chip size is $3.71{\times}1.3mm^2$.

• Journal of Electrical Engineering and Technology
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• v.3 no.2
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• pp.243-253
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• 2008

This paper deals with the analysis, design, and implementation of a single phase AC-DC Zeta converter with high frequency transformer isolation and power factor correction(PFC) in two modes of operation, discontinuous current mode of operation(DCM), and continuous current mode of operation(CCM). A Digital Signal Processor(DSP) based implementation is carried out for validation of the Zeta converter developed design in discontinuous mode of operation. A comparison of both modes of operation is presented for a 1kW power rating from the point of view of steady state and dynamic behavior, power quality, simplicity, control technique, device rating, and converter size. The experimental results of a developed prototype of Zeta converter are presented for validation of the developed design. It is observed that CCM is most suitable for higher power applications where it requires some complex control and sensing of the additional variables.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.638-646
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• 2005

In recent wireless communications, direct conversion transceiver or If sampling SDR-based receivers have being designed as an alternative to conventional transceiver topologies. In direct conversion receiver a.chitectu.e, the 1.equency/phase offset between the RF input signal and the local oscillator signal is a major impairment factor even though the conventional AFC/APC compensates the service deterioration due to the offset. To rover the limited tracking range of the conventional method and effectively aid compensation scheme in terms of I/Q channel imbalances, the frequency/phase offset compensation in RF-front end signal stage is proposed in this paper. In RF-front end, the varying phase offset besides the fixed large frequency/phase offset are corrected by using early-late phase compensator. A more simple frequency and phase tacking function in digital signal processing stage of direct conversion receiver is effectively available by an ingenious frequency/phase offset tracking method in RF front-end stage.

• Smart Media Journal
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• v.12 no.5
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• pp.65-72
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• 2023

Smart Farm means creating new value in various fields related to agriculture, including not only agricultural production but also distribution and consumption through the convergence of agriculture and ICT. In Korea, a rental smart farm is created to spread smart agriculture, and a smart farm big data platform is established to promote data collection and utilization. It is pushing for digital transformation of agricultural products distribution from production areas to consumption areas, such as expanding smart APCs, operating online exchanges, and digitizing wholesale market transaction information. As such, although agricultural data is generated according to characteristics from various sources, it is only used as a service using statistics and standardized data. This is because there are limitations due to distributed data collection from agriculture to production, distribution, and consumption, and it is difficult to collect and process various types of data from various sources. Therefore, in this paper, we analyze the current state of domestic agricultural data collection and sharing for digital agriculture and propose a data collection and linkage method for artificial intelligence services. And, using the proposed data, we propose a deep learning-based environmental factor recommendation method.

• Genomics & Informatics
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• v.17 no.4
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• pp.42.1-42.6
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• 2019

Robust identification of genetic alterations is important for the diagnosis and subsequent treatment of tumors. Screening for genetic alterations using tumor tissue samples may lead to biased interpretations because of the heterogeneous nature of the tumor mass. Liquid biopsy has been suggested as an attractive tool for the non-invasive follow-up of cancer treatment outcomes. In this study, we aimed to verify whether the mutations identified in primary tumor tissue samples could be consistently detected in plasma cell-free DNA (cfDNA) by digital polymerase chain reaction (dPCR). We first examined the genetic alteration profiles of three colorectal cancer (CRC) tissue samples by targeted next-generation sequencing (NGS) and identified 11 non-silent amino acid changes across six cancer-related genes (APC, KRAS, TP53, TERT, ARIDIA, and BRCA1). All three samples had KRAS mutations (G12V, G12C, and G13D), which were well-known driver events. Therefore, we examined the KRAS mutations by dPCR. When we examined the three KRAS mutations by dPCR using tumor tissue samples, all of them were consistently detected and the variant allele frequencies (VAFs) of the mutations were almost identical between targeted NGS and dPCR. When we examined the KRAS mutations using the plasma cfDNA of the three CRC patients by dPCR, all three mutations were consistently identified. However, the VAFs were lower (range, 0.166% to 2.638%) than those obtained using the CRC tissue samples. In conclusion, we confirmed that the KRAS mutations identified from CRC tumor tissue samples were consistently detected in the plasma cfDNA of the three CRC patients by dPCR.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.760-770
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• 2016

A 12-bit 750 kS/s Dual-Sampling Successive Approximation Register Analog-to-Digital Converter (SAR ADC) technique with reduced Capacitive DAC (CDAC) is presented in this paper. By adopting the Adaptive Power Control (APC) technique for the two-stage latched type comparator and using bootstrap switch, power consumption can be reduced and overall system efficiency can be optimized. Bootstrapped switches also are used to enhance the sampling linearity at a high input frequency. The proposed SAR ADC reduces the average switching energy compared with conventional SAR ADC by adopting reduced the Most Significant Bit (MSB) cycling step with Dual-Sampling of the analog signal. This technique holds the signal at both comparator input asymmetrically in sample mode. Therefore, the MSB can be calculated without consuming any switching energy. The prototype SAR ADC was implemented in $0.18-{\mu}m$ CMOS technology and occupies $0.728mm^2$. The measurement results show the proposed ADC achieves an Effective Number-of-Bits (ENOB) of 10.73 at a sampling frequency of 750 kS/s and clock frequency of 25 MHz. It consumes only 0.13 mW from a 5.0-V supply and achieves the INL and DNL of +2.78/-2.45 LSB and +0.36/-0.73 LSB respectively, SINAD of 66.35 dB, and a Figures-of-Merit (FoM) of a 102 fJ/conversion-step.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.274-286
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• 2016

This paper presents a 4-channel multi-rate vertical-cavity surface-emitting laser (VCSEL) driver. In order to keep the output power constant with respect to the process, voltage, temperature (PVT) variations, this research proposes automatic power and magnitude. For the fast settling time, the high-speed 10-bit time-interleaved Flash-successive approximation analog to digital converter (Flash-SAR ADC) is proposed and shared for automatic power and magnitude calibration to reduce the die area and power consumption. This chip is fabricated using $0.13-{\mu}m$ CMOS technology and the die area is $4.2mm^2$. The power consumption is 117.84 mW per channel from a 3.3 V supply voltage at 10 Gbps. The measured resolution of bias /modulation current for APC/AMC is 0.015 mA.