• Title/Summary/Keyword: dual modules

Search Result 99, Processing Time 0.038 seconds

Image System Using Dual Energy Detector (이중 에너지 검출기를 이용한 영상 시스템)

  • Yeo, Hwa-Yeon
    • Journal of the Korea Academia-Industrial cooperation Society
    • /
    • v.11 no.9
    • /
    • pp.3517-3523
    • /
    • 2010
  • Single exposure dual X-ray imaging can be used to separate soft and dense-material images for medical and industrial applications. This study keep focusing baggage inspection system(BIS) specifically. New detector modules for single exposure dual X-ray imaging are consisted of low energy detector (LED) and high energy detector (HED). First, the optimized thickness of copper filter coupled HED to separate low energy and high energy was simulated by the given X-ray energy (140 kVp, 1 mA) using Monte Carlo simulation codes, MCNPX. So as a result of simulation, the copper filter thickness is 0.7 mm. For the design of PIN photodiode, ATLAS device simulation tool was used. 16 channels PIN photodiode of 1.5 mm ${\times}$ 3.2 mm for Dual X-ray imaging detector was fabricated in the process of ETRI. And its dark current and quantum efficiency, terminal capacitance were measured. It was proven that the Lanex Fast B coupled HED were a sufficient candidate to replace the CsI(Tl) commerced in dual X-ray system, since these give a strong signal, overcoming system noise. Finally dual X-ray image was acquired through correction of the LED X-ray Image and the HED X-ray Image.

Pipelined Scheduling of Functional HW/SW Modules for Platform-Based SoC Design

  • Kim, Won-Jong;Chang, June-Young;Cho, Han-Jin
    • ETRI Journal
    • /
    • v.27 no.5
    • /
    • pp.533-538
    • /
    • 2005
  • We developed a pipelined scheduling technique of functional hardware and software modules for platform-based system-on-a-chip (SoC) designs. It is based on a modified list scheduling algorithm. We used the pipelined scheduling technique for a performance analysis of an MPEG4 video encoder application. Then, we applied it for architecture exploration to achieve a better performance. In our experiments, the modified SoC platform with 6 pipelines for the 32-bit dual layer architecture shows a 118% improvement in performance compared to the given basic SoC platform with 4 pipelines for the 16-bit single-layer architecture.

  • PDF

Kinematic Analysis of Fault-Tolerant 3 Degree-of-Feedom Spherical Modules (고장에 강인한 구형 3자유도 모듈에 관한 기구학적 해석)

  • 이병주;김희국
    • Transactions of the Korean Society of Mechanical Engineers
    • /
    • v.18 no.11
    • /
    • pp.2846-2859
    • /
    • 1994
  • This work deals with kinematic analysis of fault-tolerant 3 degree-of-freedom spherical modules which have force redundancies in its parallel structure. The performance of a redundantly actuated four-legged module with no actuator failure, a single actuator failure, partial and half failure of dual actuator are compared to that of a three-legged module, in terms of maximum force transmission ratio, isotropic characteristics, and fault-tolerant capability. Additionally, a system with an excess number of small floating actuators is considered, and the contribution of these small actuators to the force transmission and fault-tolerant capability is evaluated. This study illustrates that the redundant actuation mode allows significant saving of input actuation effort, and also delivers a fault tolerance.

Solar Module Glass Coating Technology for Improvement of the transmittance (태양광 모듈용 Glass의 투과율 향상을 위한 Coating 기술 개발)

  • Jung, Jin-Su;Jung, In-Sung;Lee, Bum-Su;Jang, Jin-Ho;Ban, Seong-Tae;Kim, Jong-Il
    • 한국신재생에너지학회:학술대회논문집
    • /
    • 2011.05a
    • /
    • pp.120.1-120.1
    • /
    • 2011
  • Increase the efficiency of PV modules for high-efficiency solar cells, light transmittance improvements, increasing the module, and much more research and development. Dual we light transmittance for photovoltaic module materials in low iron tempered glass in SiO2 using liquid AR implementation, light transmittance to solar modules to increase the efficiency of research.

  • PDF

A Two-Step Scheduling Algorithm to Support Dual Bandwidth Allocation Policies in an Ethernet Passive Optical Network

  • Lee, Ho-Sook;Yoo, Tae-Whan;Moon, Ji-Hyun;Lee, Hyeong-Ho
    • ETRI Journal
    • /
    • v.26 no.2
    • /
    • pp.185-188
    • /
    • 2004
  • In this paper, we design a two-step scheduling algorithm to support multiple bandwidth allocation policies for upstream channel access in an Ethernet passive optical network. The proposed scheduling algorithm allows us a simultaneous approach for multiple access control policies: static bandwidth allocation for guaranteed bandwidth service and dynamic bandwidth allocation for on-demand, dynamic traffic services. In order to reduce the scheduling complexity, we separate the process of the transmission start- time decision from the process of grant generation. This technique does not require the timing information of other bandwidth allocation modules, so respective modules are free from a heavy amount of timing information or complex processing.

  • PDF

Three-Phase High-Power-Density Bidirectional DC-DC Converter (3상 변압기를 이용한 고밀도 양방향 전력변환기)

  • Le, Tuan-Vu;Choi, Woo-Seok;Kim, Sun-Pil;Park, Sung-Jun
    • Proceedings of the KIPE Conference
    • /
    • 2014.07a
    • /
    • pp.45-46
    • /
    • 2014
  • This paper presents a three-phase high-power-density bidirectional DC-DC converter. The converter employs dual three-phase active bridges and a three-phase transformer. The presented converter is controlled by two symmetric PWM modules and phase between two symmetric PWM modules to control the power flow. Simulation is included to verify the presented converter.

  • PDF

INVERTIBILITY OF GENERALIZED BESSEL MULTIPLIERS IN HILBERT C-MODULES

  • Tabadkan, Gholamreza Abbaspour;Hosseinnezhad, Hessam
    • Bulletin of the Korean Mathematical Society
    • /
    • v.58 no.2
    • /
    • pp.461-479
    • /
    • 2021
  • This paper includes a general version of Bessel multipliers in Hilbert C∗-modules. In fact, by combining analysis, an operator on the standard Hilbert C∗-module and synthesis, we reach so-called generalized Bessel multipliers. Because of their importance for applications, we are interested to determine cases when generalized multipliers are invertible. We investigate some necessary or sufficient conditions for the invertibility of such operators and also we look at which perturbation of parameters preserve the invertibility of them. Subsequently, our attention is on how to express the inverse of an invertible generalized frame multiplier as a multiplier. In fact, we show that for all frames, the inverse of any invertible frame multiplier with an invertible symbol can always be represented as a multiplier with an invertible symbol and appropriate dual frames of the given ones.

MONOIDAL FUNCTORS AND EXACT SEQUENCES OF GROUPS FOR HOPF QUASIGROUPS

  • Alvarez, Jose N. Alonso;Vilaboa, Jose M. Fernandez;Rodriguez, Ramon Gonzalez
    • Journal of the Korean Mathematical Society
    • /
    • v.58 no.2
    • /
    • pp.351-381
    • /
    • 2021
  • In this paper we introduce the notion of strong Galois H-progenerator object for a finite cocommutative Hopf quasigroup H in a symmetric monoidal category C. We prove that the set of isomorphism classes of strong Galois H-progenerator objects is a subgroup of the group of strong Galois H-objects introduced in [3]. Moreover, we show that strong Galois H-progenerator objects are preserved by strong symmetric monoidal functors and, as a consequence, we obtain an exact sequence involving the associated Galois groups. Finally, to the previous functors, if H is finite, we find exact sequences of Picard groups related with invertible left H-(quasi)modules and an isomorphism Pic(HMod) ≅ Pic(C)⊕G(H∗) where Pic(HMod) is the Picard group of the category of left H-modules, Pic(C) the Picard group of C, and G(H∗) the group of group-like morphisms of the dual of H.

A Simple Capacitor Voltage Balancing Method with a Fundamental Sorting Frequency for Modular Multilevel Converters

  • Peng, Hao;Wang, Ying;Wang, Kun;Deng, Yan;He, Xiangning;Zhao, Rongxiang
    • Journal of Power Electronics
    • /
    • v.14 no.6
    • /
    • pp.1109-1118
    • /
    • 2014
  • A Fundamental Frequency Sorting Algorithm (FFSA) is proposed in this paper to balance the voltages of floating dc capacitors for Modular Multilevel Converters (MMCs). The main idea is to change the sequences of the CPS-PWM carriers according to the capacitor voltage increments during the previous fundamental period. Excessive frequent sorting is avoided and many calculating resources are saved for the controller. As a result, more sub-modules can be dealt with. Furthermore, it does not need to measure the arm currents. Therefore, the communication between the controllers can be simplified and the number of current sensors can be reduced. Moreover, the proposed balancing method guarantees that all of the switching frequencies of the sub-modules are equal to each other. This is quite beneficial for the thermal design of the sub-modules and the lifetime of the power switches. Simulation and experimental results acquired from a 9-level prototype verify the viability of the proposed balancing method.

Performance Characteristics of a Chirp Data Acquisition and Processing System for the Time-frequency Analysis of Broadband Acoustic Scattering Signals from Fish Schools (어군에 의한 광대역 음향산란신호의 시간-주파수 분석을 위한 chirp 데이터 수록 및 처리 시스템의 성능특성)

  • Lee, Dae-Jae
    • Korean Journal of Fisheries and Aquatic Sciences
    • /
    • v.51 no.2
    • /
    • pp.178-186
    • /
    • 2018
  • A chirp-echo data acquisition and processing system was developed for use as a simplified, PC-based chirp echo-sounder with some data processing software modules. The design of the software and hardware system was implemented via a field-programmable gate array (FPGA). Digital signal processing algorithms for driving a single-channel chirp transmitter and dual-channel receivers with independent TVG (time varied gain) amplifier modules were incorporated into the FPGA for better real-time performance. The chirp-echo data acquisition and processing system consisted of a notebook PC, an FPGA board, and chirp sonar transmitter and receiver modules, which were constructed using three chirp transducers operating over a frequency range of 35-210 kHz. The functionality of this PC-based chirp echo-sounder was tested in various field experiments. The results of these experiments showed that the developed PC-based chirp echo-sounder could be used in the acquisition, processing and analysis of broadband acoustic echoes related to fish species identification.