• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.10
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• pp.1905-1913
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• 2006

The researches about the hardware and the software implementing ubiquitous sensor network have great rush in recent years. This paper deals the development of a sensor node with the dual interface which also has an RF wireless interface while has an Bluetooth interface used widely in present. This sensor node includes a Atmeg32 microcontroller, a Bluetooth module, a RF module. a temperature-humidity sensor. and I also develop the F/Ws controlling each modules with C language using GCC compiler. The sensor node developed can reaches 15m with Bluetooth interface and 60m with RF interface. It works stably with the voltage above 5V and it consumes currents 21mA average in idle mode, 63mA average in active mode.

• Journal of Power Electronics
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• v.1 no.2
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• pp.78-87
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• 2001

A new high-power step-up based on the two-module parallel-input (PISO) modular dual inductor-fed push-pull converter is proposed. The proposed converter is operated at a constant duty cycle and employs and auxiliary circuit to control the output voltage with a phase-shift between two modules. It shows a high efficiency due to the greatly reduced switch turn-off stress. It also shows a high and linear voltage conversion ratio, low current stress in the output capacitor, and fast control-to-output dynamics. The operation principles and the mathematical models of the proposed converter are presented. Features of the proposed converter are discussed in comparison with the two-module PISO modular dual inductor-fed push-pull converter. Also, experimental results from a 50kHz, 800W, 350 Vdc prototype with an input voltage range of 20-32 Vdc are provided to confirm the validity of the proposed converter. The new converter compares favorably with the conventional counterpart, and is considered well siuted to high-power step-up applications.

• Journal of Power Electronics
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• v.7 no.3
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• pp.246-256
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• 2007

In this paper, a novel type auxiliary active edge resonant snubber assisted zero current soft switching pulse modulation Single-Ended Push Pull (SEPP) series load resonant inverter using IGBT power modules is proposed for cost effective consumer high-frequency induction heating (IH) appliances. Its operating principle in steady state is described by using each switching mode's equivalent operating circuits. The new multi resonant high-frequency inverter with series load resonance and edge resonance can regulate its high frequency output power under a condition of a constant frequency zero current soft switching (ZCS) commutation principle on the basis of the asymmetrical pulse width modulation (PWM) control scheme. Brand-new consumer IH products using the proposed ZCS-PWM series load resonant SEPP high-frequency inverter using IGBTs is evaluated and discussed as compared with conventional high-frequency inverters on the basis of experimental results. In order to extend ZCS operation ranges under a low power setting PWM as well as to improve efficiency, the high frequency pulse density modulation (PDM) strategy is demonstrated for high frequency multi-resonant inverters. Its practical effectiveness is substantially proved from an application point of view.

• Journal of Radiation Industry
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• v.5 no.4
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• pp.313-316
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• 2011

[$^{18}F$]FDG (2-[$^{18}F$] Fluoro-2-deoxy-D-Glucose), which is required Automated Synthetic Module for production, is most often used Radiopharmaceuticals in nuclear medicine. In this study, an Automated Synthesis Module was developed to produce FDG in two consecutive time when F-18 feds continuously by modifying a domestic FDG Automated Synthetic Module on structural geometry and control system. The results were showed that the Average Synthesis Yields on the developed Automated Synthetic Module were $45{\pm}3%$ (n=20), $50{\pm}3%$ (n=20) respectively. The Quality Control results, such as Radio TLC, Radiochemical purity, Gamma-counter, pH, LAL Test, Micro bacteria test, showed in same level with domestic [$^{18}F$]FDG Auto-Synthetic modules. Therefore, if some features were improved by considering the components life time and appearance, commercial sales can be expected because of low price and easy maintenance compared with foreign products.

• Proceedings of the Korean Society of Medical Physics Conference
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• 2003.09a
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• pp.44-44
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• 2003

As a basic measurement tool in the areas of animal models of human disease, gene expression and therapy, and drug discovery and development, small animal PET imaging is being used increasingly. An ideal small animal PET should have high sensitivity and high and uniform resolution across the field of view to achieve high image quality. However, the combination of long narrow pixellated crystal array and small ring diameter of small animal PET leads to the degradation of spatial resolution for the source located at off center. This degradation of resolution can be improved by determining the depth of interaction (DOI) in the crystal and by taking into account the information in sorting the coincident events. Among a number of 001 identification schemes, dual layer phsowich detector has been widely investigated by many research groups due to its practicability and effectiveness on extracting DOI information. However, the effects of each crystal length composing dual layer phoswich detector on DOI measurements and image qualities were not fully characterized. In order to minimize the DOI effect, the length of each layer of phoswich detector should be optimized. The aim of this study was to perform simulations using a simulation tool, GATE to design the optimum lengths of crystals composing a dual layer phoswich detector. The simulated small PET system employed LSO front layer LuYAP back layer phoswich detector modules and the module consisted of 8${\times}$8 arrays of dual layer crystals with 2 mm ${\times}$ 2 mm sensitive area coupled to a Hamamatsu R7600 00 M64 PSPMT. Sensitivities and variation of radial resolutions were simulated by varying the length of LSO front layer from 0 to 10 mm while the total length (LSO + LuYAP) was fixed to 20 mm for 10 cm diameter ring scanner. The radial resolution uniformity was markedly improved by using DOI information. There existed the optimal lengths of crystal layers to minimize the variation of radial resolutions. In 10 cm ring scanner configuration, the radial resolution was kept below 3.4 mm over 8 cm FOV while the sensitivity was higher than 7.4% for LSO 5 mm : LuYAP 15 mm phoswich detector. In this study, the optimal length of dual layer phoswich detector was derived to achieve high and uniform radial resolution.

• Journal of Power Electronics
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• v.4 no.3
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• pp.138-151
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• 2004

In this paper, a constant frequency phase shifting PWM-controlled voltage source full bridge-type series load resonant high-frequency inverter using the $4^{th}$ generation IGBT power modules is presented for innovative consumer electromagnetic induction heating applications, such as a hot water producer, steamer and super heated steamer. The bridge arm side link passive capacitive snubbers in parallel with each power semiconductor device and AC load side linked active edge inductive snubber-assisted series load resonant tank soft switching inverter with a constant frequency phase shifted PWM control scheme is evaluated and discussed on the basis of the simulation and experimental results. It is proved from a practical point of view that the series load resonant and edge resonant hybrid high-frequency inverter topology, what is called, DE class type, including the variable-power variable-frequency regulation function can expand zero voltage soft switching commutation area even under low output power setting ranges, which is more suitable and acceptable for newly developed induction heated dual pack fluid heaters. Furthermore, even the lower output power regulation mode of this high-frequency load resonant tank inverter circuit is verified so that this inverter can achieve ZVS with the aid of the single auxiliary inductor snubber.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.774-777
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• 2005

In this paper, a constant frequency phase shifting PWM controlled voltage source full bridge-type series load resonant high-frequency inverter using the IGBT power modules is presented for innovative consumer electromagnetic induction heating applications such as a hot water producer, steamer and super heated steamer. The full bridge arm side link passive quasi-resonant capacitor snubbers in parallel with the each power semiconductor device and high frequency AC load side linked active edge inductive snubber-assisted series load resonant tank soft switching inverter with a constant frequency phase shifted PWM control scheme is discussed and evaluated on the basis of the simulation and experimental results. It is proved from a practical point of view that the series load resonant and edge resonant hybrid high-frequency soft switching PWM inverter topology, what is called class DE type. including the variable-power variable-frequency(VPVF) regulation function can expand zero voltage soft switching commutation range even under low output power setting ranges, which is more suitable and acceptable for induction heated dual packs fluid heater developed newly for consumer power utilizations. Furthermore, even in the lower output power regulation mode of this high-frequency load resonant tank high frequency inverter circuit it is verified that this inverter can achieve ZVS with the aid of the single auxiliary inductor snubber.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.9
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• pp.26-34
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• 1998

This paper presents a characterization method for faults of circuit patterns on MCM(Multichip Module) or PCB(Printed Circuit Board) substrates with electron beams of a SEM(Scanning Electron Microscope) by inducing voltage contrast on the signal line. The experimentation employes dual potential electron beams for the fault characterization of circuit patterns with a commercial SEM without modifying its structure. The testing procedure utilizes only one electron gun for the generation of dual potential electron beams by two different accelerating voltages, one for charging electron beam which introduces the yield of secondary electron $\delta$ < 1 and the other for reading beam which introduces $\delta$ > 1. Reading beam can read open's/short's of a specific net among many test nets, simultaneously discharging during the reading process for the next step, by removing its voltage contrast. The experimental results of testing the copper signal lines on glass-epoxy substrates showed that the state of open's/short's had generated the brightness contrast due to the voltage contrast on the surface of copper conductor line, when the net had charged with charging electron beams of 7KV accelerating voltages and then read with scanning reading electron beams of 2KV accelerating voltages in 10 seconds. The experimental results with Au pads of a IC die and Au plated Cu pads of BGA substrates provided the simple test method of circuit lines with 7KV charging electron beam and 2KV reading beam. Thus the characterization method showed that we can test open and short circuits of the net nondestructively by using dual potential electron beams with one SEM gun.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.287-289
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• 2011

본 논문은 인피니언 테크놀로지스의 RC-IGBT (Reverse Conducting Isolated Gate Bipolar Transistor)와 SOI 드라이브 IC(Integrated Circuit)를 사용한 DIL(Dual-In-Line) 구조의 저전력 모듈인 CIPOS TM (Control Integrated POwer System) 제품을 소개한다. 이 전력 모듈은 최적의 게이트 구동회로, 트렌치 필드스톱의 RC-IGBT를 사용하여 기존의 IGBT 와 Diode를 사용하는 구조에서 최소화 된 패키지 크기를 사용하여 높은 효율을 구현할 수 있다. 본 논문을 통하여 인버터의 어플리케이션에 적합하게 설계된 전력모듈에 대한 소개와 그 특징 및 시스템 구성을 위한 고려사항에 대하여 기술하였다.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.859-862
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• 2003

This paper proposes an emulation environment for SoC designs using small number of large gate-count FPGA's and a PC system. To overcome the pin limitation problem in partitioning the design when the design size overwhelms the FPGA gate count, we use bus splitter modules that replicate on-chip bus signals in one FPGA to arbitrary number of other FPGA's with minimal pin count. The proposed scheme is applied to the emulation of 2 million gate multimedia processing chip using two Xilinx Viretex-2 6000 FPGA devices in 6.6MHz operating frequency. An ARM core, memories, camera and LCD display are modeled in software using dual 2GHz Pentium-III processors. This scheme can be utilized for more than 2 FPGA's in the same ways as two FPGA case without losing emulation speed.