• The Transactions of the Korea Information Processing Society
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• v.6 no.12
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• pp.3634-3641
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• 1999

LAN Emulation and IPOA are the two most widei y accepted network protocols which allow to provide conventional LAN-based data services on ATM LAN environment. In this paper, the performance of IPOA and LAN Emulation on ATM LAN testbed is compared and the results are compared with performance of Ethernet as well. For performance comparison, metrics such as application throughput, latency, CPU usage are used. In addition, a network program that uses the socket based TCP/IP application programming interface to send large data files from client to server via ATM LAN switch is developed. IPOA provides lower latency and higher throughput than LAN Emulation while LAN Emulation consumes more CPU usage.

• Journal of Korean Society of Archives and Records Management
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• v.14 no.3
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• pp.55-82
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• 2014

The objective of this research is to show the possibilities of emulation strategy in the long-term preservation for the digital components of Korean public agencies. First, this study analyzed four major emulation projects that were conducted in the world, such as CAMiLEON, KB, Planets and KEEP. Second, it compared the three different emulation approaches, such as device emulation, OS emulation and application emulation. Third, it searched all the digital components that one public agency produced during the last six years. Through the search, this study found out that the HWP and XLS format files comprised around 90% of the files. Fourth, it examined the functionalities of the formats, which may have been lost when the format was converted to PDF/A. Last, this study introduced the two prototype emulators for the National Archives of Korea. One is a type of OS emulator, while the other is a type of application emulator.

• Information and Communications Magazine
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• v.13 no.3
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• pp.61-70
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• 1996

In this paper, the architecture of the LAN Emulation service defined by the ATM Forum is introduced. In order to use the vast base of the existing LAN application software in ATM network. LAN Emulation provides a MAC layer service emulating connectionless services of legacy LANs on ATM networks. LAN Emulation forms a logical overlay network, called and emulated LAN, on top of an ATM network. LAN Emulation service comprises a set of LAN Emulation Clients(LECs) residing in end stations of an emulated LAN and three logical service entities : LAN Emulation Configuration Server (LECS), LAN Emulation Server(LES). and Broadcast and Unknown Server(BUS). LEC utilizes the services provided by these three servers to provide seamless interworking between legacy LANs and ATM networks, and to support transparent communications between LAN applications over ATM.

• Journal of the Optical Society of Korea
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• v.12 no.2
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• pp.69-78
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• 2008

EPONs are a low cost, high speed solution to the bottleneck problem of broadband access networks. To support point-to-point and shared LAN emulation, EPONs use the multi-point control protocol (MPCP), which uses logical link identification (LLID) forframe tagging and filtering between the OLT and ONUs. In this paper, ONU-based multicast or multiple shared LAN emulation for IPTV services is proposed using logical group identification (LGID). Using ONUbased VLAN services, EPONs can support separate and secure connections between providers and subscribers in a simple manner. Also, differentiated IPTV channel packages can be delivered through EPONs by implementing ONU-based VLAN and IGMP snooping mechanisms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.91-103
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• 2002

For massive FPGA based emulator, the interconnection architecture and the transmission method of signals between FPGA's are important elements which decide speed of emulation and extendability of emulator. Existing FPGA-based emulation system is faced the problems of which the emulation speed getting slow drastically as the complexity of circuit increases. In this paper, we proposed a new innovative emulation architecture that has high resource usage rate and makes the fast emulation Possible. The emulator with very unique hierarchical ring topology Presented here has merits to overcome FPGA pin limitation by connecting each FPGA into a set of pipelined rings, and it also makes emulation speed at the tens of MHz at least even at system level where the verification complexity can easily exceed the verification capability of designers.

• Journal of the Korea Society of Computer and Information
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• v.17 no.2
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• pp.1-11
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• 2012

Recently, we have seen several implementations that virtualize the ARM architecture. Since the current ARM architecture is not possible to be virtualized using the traditional technique called "trap-and-emulation", we usually detect all virtualization sensitive instructions during the run-time of a guest kernel and emulate them virtually rather than executing them directly. The emulation for virtualization is usually implemented either by binary translation or interpretation. Our research is about how to improve the performance of emulation for virtualization based on interpretation. The interpretation usually requires a few steps: instruction fetching, instruction decoding and instruction executing. In this paper, we propose a method that decodes all virtualization sensitive instructions during the compilation time of a guest kernel and reduces the time required for interpretation during the run time of the guest kernel. Our method provides both implementation simplicity and performance improvement of emulation for virtualization based on interpretation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.17-28
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• 1999

In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.859-862
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• 2003

This paper proposes an emulation environment for SoC designs using small number of large gate-count FPGA's and a PC system. To overcome the pin limitation problem in partitioning the design when the design size overwhelms the FPGA gate count, we use bus splitter modules that replicate on-chip bus signals in one FPGA to arbitrary number of other FPGA's with minimal pin count. The proposed scheme is applied to the emulation of 2 million gate multimedia processing chip using two Xilinx Viretex-2 6000 FPGA devices in 6.6MHz operating frequency. An ARM core, memories, camera and LCD display are modeled in software using dual 2GHz Pentium-III processors. This scheme can be utilized for more than 2 FPGA's in the same ways as two FPGA case without losing emulation speed.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.10a
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• pp.261-261
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• 2003

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.10
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• pp.2180-2186
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• 2010

As the substantial increase in battlefield density, multiple and complex weapon systems, Ensuring the Survivability of the platform has been emphasized. Most of platforms have equipped with ASE (Aircraft Survivability Equipment) system in order to protect the platform and operator against at modernized hostile weapon. ASE system enhance the survivability of the platform through providing accurate situation awareness information by detecting and countermeasuring hostile threats. One of Key factor of the AE system performance is handling multiple and complex threats. In this study, it describes the fact that the performance of ASE system with proposed threat integration algorithm is verified in the developed threat emulation system and also, suggests system verification method before deployment by dealing with complex threat situation.