• Title/Summary/Keyword: fanout

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Multicast Switch for High Speed Packet Transmission (고속 패킷 전송을 위한 멀티캐스트 스위치)

  • 손동욱;손유익
    • Proceedings of the Korean Information Science Society Conference
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    • 2001.10c
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    • pp.412-414
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    • 2001
  • 본 논문은 초고속통신망에서 멀티캐스트 스위칭에서 발생될 수 있는 오버플로우 문제와 블로킹 문제를 보다 효율적으로 해결하고, 공정하게 입력포트에 접근함으로 작은 fanout에 대한 불공정성을 해결하기 위한 멀티캐스트 스위치를 제안하고자 한다. 제안된 스위치는 셀 분할(cell pre-splitting)과 공유된 버퍼, Group Spliiting, 그리고 그룹분할망으로 구성되어지며, 큰 fanout에 대한 작은 fanout을 가진 입력포트에 도착한 패킷의 불공정한 대우를 해결하여 시스템 전체 지연 시간을 줄여 산출량을 극대화할 수 있다.

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Fanout Constrained Logic Synthesis (Fanout 제약 조건하의 논리 회로 합성)

  • 이재형;황선영
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.28A no.5
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    • pp.387-397
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    • 1991
  • This paper presents the design and implementation of a performance-driven logic synthesis system that automatically generates circuits satisfying the given timing and fanout constraints in minimal silicon area. After performing technology independent and dependent optimization, the system identifies and resynthesizes the gates with large loading delay due to excessive fanouts to eliminate the critical path. Experimental results for MCNC benchmark circuits show that proposed system generates the circuits with less delay by up to 20%.

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A Fair Multicast Switch under Nonuniform Traffic (비균일 트래픽하의 공정한 멀티캐스트 스위치)

  • Son, Dong-Wuk;Son, Yoo-Ek
    • Proceedings of the Korea Information Processing Society Conference
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    • 2001.04a
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    • pp.535-538
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    • 2001
  • 본 논문은 작은 fanout에 대한 불공정성과 hot-spot의 문제를 해결하기 위해 공정하게 입력포트에 접근하여 복사망으로 들어갈 수 있는 멀티캐스트 스위치를 제안하고자 한다. 제안된 스위치는 큰 fanout에 대한 작은 fanout을 가진 입력포트에 도착한 패킷의 불공정한 대우를 해결하여 시스템 전체 지연시간을 줄여 산출량을 극대화할 수 있다.

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A Test Vector Reordering for Switching Activity Reduction During Test Operation Considering Fanout (테스트시 스위칭 감소를 위해 팬 아웃을 고려한 테스트벡터 재 정렬)

  • Lee, Jae-Hoon;Baek, Chul-Ki;Kim, In-Soo;Min, Hyoung-Bok
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.60 no.5
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    • pp.1043-1048
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    • 2011
  • Test vector reordering is a very effective way to reduce power consumption during test application. But, it is time-consuming and complicated processes, and it does not consider internal circuit structure, which may limit the effectiveness. In this paper, we order test vectors using fanout count of primary inputs that consider the internal circuit structure, which may reduce the switching activity. Then, we reorder test test vectors again by using Hamming distance between test vectors. We proposed FOVO algorithm to perform these two ideas. FOVO is an effective way to reduce power consumption during test application. The algorithm is applied to benchmark circuits and we get an average of 3.5% or more reduction of the power consumption.

Topology-Aware Fanout Set Division Scheme for QoS-Guaranteed Multicast Transmission

  • Kim, Kyungmin;Lee, Jaiyong
    • Journal of Communications and Networks
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    • v.15 no.6
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    • pp.614-634
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    • 2013
  • The proliferation of real-time multimedia services requires huge amounts of data transactions demanding strict quality-of-service (QoS) guarantees. Multicast transmission is a promising technique because of its efficient network resource utilization. However, high head-of-line (HOL) blocking probability and lack of service-specific QoS control should be addressed for practical implementations of multicast networks. In this paper, a topology aware fanout set division (TAFD) scheme is proposed to resolve these problems. The proposed scheme is composed of two techniques that reduce HOL blocking probability and expedite packet delivery for large-delay branches regarding multicast tree topology. Since management of global topology information is not necessary, scalability of the proposed scheme is guaranteed. Mathematical analysis investigates effects of the proposed scheme and derives optimal operational parameters. The evaluation results show that the TAFD scheme achieves significant delay reduction and satisfies required delay bounds on various multicast networks.

Buffer Insertion-based HFNS for Efficient ASIC Implementation (효율적인 ASIC구현을 위한 버퍼 삽입 방식의 HFNS)

  • Jang, Seok Woo;Kim, Dong-Wook;Seo, Young-Ho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.2
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    • pp.415-424
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    • 2014
  • In this paper, we proposed a practical methodology of HFNS (high fanout net synthesis) to use buffer insertion which has been applied in the fields. First, we proposed consideration to execute HFNS and detail techniques for it. Next we proposed post-process method which is necessary to obtain success of HFNS. The buffer-insertion based method for HFNS is a kind of popular technique, but we targeted a practical and commercial aspect of HHNS.

DIMPLE-II: Dynamic Membership Protocol for Epidemic Protocols

  • Sun, Jin;Choi, Byung-K.;Jung, Kwang-Mo
    • Journal of Computing Science and Engineering
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    • v.2 no.3
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    • pp.249-273
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    • 2008
  • Epidemic protocols have two fundamental assumptions. One is the availability of a mechanism that provides each node with a set of log(N) (fanout) nodes to gossip with at each cycle. The other is that the network size N is known to all member nodes. While it may be trivial to support these assumptions in small systems, it is a challenge to realize them in large open dynamic systems, such as peer-to-peer (P2P) systems. Technically, since the most fundamental parameter of epidemic protocols is log(N), without knowing the system size, the protocols will be limited. Further, since the network churn, frequently observed in P2P systems, causes rapid membership changes, providing a different set of log(N) at each cycle is a difficult problem. In order to support the assumptions, the fanout nodes should be selected randomly and uniformly from the entire membership. This paper investigates one possible solution which addresses both problems; providing at each cycle a different set of log(N) nodes selected randomly and uniformly from the entire network under churn, and estimating the dynamic network size in the number of nodes. This solution improves the previously developed distributed algorithm called Shuffle to deal with churn, and utilizes the Shuffle infrastructure to estimate the dynamic network size. The effectiveness of the proposed solution is evaluated by simulation. According to the simulation results, the proposed algorithms successfully handle network churn in providing random log(N0 fanout nodes, and practically and accurately estimate the network size. Overall, this work provides insights in designing epidemic protocols for large scale open dynamic systems, where the protocols behave autonomically.

A New Logic Transformation Method for Both Low Power and High Testability (저 전력소모와 높은 테스트용이성을 위한 새로운 논리 변환 방법)

  • 손윤식;정정화
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.9
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    • pp.692-701
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    • 2003
  • In this paper, a new logic transformation method to consider both low power consumption and high testability is proposed. We search the CFF(Compact Fanout Free) that has low probability of being observable at the primary outputs. Under the condition that the CFF is unobservable at all primary outputs, the switching operations in it can be removed by adding redundant connections into it. The testability of the transformed circuit generally tends to reduce. In our method, however, the inserted redundant connections operate as test points in the test mode and can improve not only the controllability but also the observability of the CFF. The transformed circuit consumes less power in the normal mode and also has higher testability in the test mode. To show the efficiency of the proposed logic transformation method, we perform some experiments on the MCNC benchmark test circuits. The results show that the power consumption of the transformed circuit is reduced by 13% maximally and the fault coverage of the transformed circuit is increased.

External Merge Sorting in Tajo with Variable Server Configuration (매개변수 환경설정에 따른 타조의 외부합병정렬 성능 연구)

  • Lee, Jongbaeg;Kang, Woon-hak;Lee, Sang-won
    • Journal of KIISE
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    • v.43 no.7
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    • pp.820-826
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    • 2016
  • There is a growing requirement for big data processing which extracts valuable information from a large amount of data. The Hadoop system employs the MapReduce framework to process big data. However, MapReduce has limitations such as inflexible and slow data processing. To overcome these drawbacks, SQL query processing techniques known as SQL-on-Hadoop were developed. Apache Tajo, one of the SQL-on-Hadoop techniques, was developed by a Korean development group. External merge sort is one of the heavily used algorithms in Tajo for query processing. The performance of external merge sort in Tajo is influenced by two parameters, sort buffer size and fanout. In this paper, we analyzed the performance of external merge sort in Tajo with various sort buffer sizes and fanouts. In addition, we figured out that there are two major causes of differences in the performance of external merge sort: CPU cache misses which increase as the sort buffer size grows; and the number of merge passes determined by fanout.

Untestable Faults Identification Using Critical-Pair Path (임계-쌍 경로를 이용한 시험 불가능 결함의 확인)

  • 서성환;안광선
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.10
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    • pp.29-38
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    • 1999
  • This paper presents a new algorithm RICP(Redundancy Identification using Critical-pair Paths) to identify untestable faults in combinational logic circuits. In a combinational logic circuit, untestable faults occurred by redundancy of circuits. The redundancy of a circuit can be detected by analyzing areas of fanout stem and reconvergent gates. The untestable faults are identified by analyzing stem area using Critical-Pair path which is an extended concept of critical path. It is showed that RICP is better than FIRE(Fault Independent REdundancy identification) algorithm in efficiency. The performance of both algorithms was compared using ISCAS85 bench mark testing circuits.

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