• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.509-512
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• 1999

Ferroelectric Sr$_2$(Nb, Ta)$_2$O$_{7}$(SNTO), La$_2$Ti$_2$O$_{7}$(LTO) thin films were prepared by sol-gel processes. SNTO, LTO thin films were spin-coated on Pt/TiO$_2$/SiO$_2$/Si(100). Pt/Ti/SiO$_2$/Si(100). PT/ZrO$_2$/SiO$_2$/Si(100) substrates. After multiple coating, dried thin films were heat-treated for decomposition of residual organics and crystallization. Dielectric and other relevant electrical properties were measured and the results showed a little possibility in ferroelectric gate random access memory devices.ces.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.335-338
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• 1998

Ferroelectric Sr$_2$(Nb,Ta)$_2$O$_{7}$ (SNTO) thin films were prepared by chemical solution deposition processes. SNTO thin films were spin-coated on Pt/Ti/SiO$_2$/(100)Si substrates. After multiple coating, dried thin films were heat-treated for decomposition of residual organics and crystallization. B site-rich impurity phase, i.e. [Sr(Nb,Ta)$_2$O$_{6}$], was found after annealing, where its appearance was dependent on process temperature indicating the possible reaction with substrate. Dielectric and other relevant electrical properties were measured and the results showed a little possibility in ferroelectric gate random access memory devices.s.s.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.3
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• pp.213-225
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• 2002

Metal-Ferroelectric- Insulator- Silicon (MFIS) structured field effect transistor (FET) device was fabricated and characterized. Important issues to realize ferroelectric gate field effect transistor device were summarized in three sections. The choice of interlayer dielectric was made in the consideration of device functionality and chemical reaction between ferroelectric materials and silicon surface during fabrication process. Also, various ferroelectric thin film materials were taken into account to meet desired memory window and process compatibility. Finally, MFIS structured FET device was fabricated and important characteristics were discussed. For feasible integration of current device as random access memory array cell address schemes were also suggested.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.1-14
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• 2001

Current status and prospects of FET-type FeRAMs (ferroelectric random access memories) are reviewed. First, it is described that the most important issue for realizing FET-type FeRAMs is to improve the data retention characteristics of ferroelectric-gate FETs. Then, necessary conditions to prolong the retention time are discussed from viewpoints of materials, device structure, and circuit configuration. Finally, recent experimental results related to the FET-type memories are introduced, which include optimization of a buffer layer that is inserted between the ferroelectric film and a Si substrate, development of a new ferroelectric film with a small remnant polarization value, proposal and fabrication of a 1T2C-type memory cell with good retention characteristics, and so on.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.3
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• pp.73-77
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• 2023

In this study, we developed a Multi-level FeRAM (Ferroelectrics random access memory) device utilizing different ferroelectric materials and analyzed its operation through C-V analysis using simulations. To achieve Multi-level operation, we proposed an MFM (Multi-Ferroelectric Material) structure by depositing two different ferroelectric materials with distinct properties horizontally on the same bottom electrode and subsequently adding a gate electrode on top. By analyzing C-V peaks based on the polarization phenomenon occurring under different voltage conditions for the two materials, we confirmed the feasibility of achieving Multi-level operation, where either one or both of the materials can be polarized. Furthermore, we validated the process for implementing the proposed structure using semiconductor fabrication through process simulations. These results signify the significance of the new structure as it allows storing multiple states in a single memory cell, thereby greatly enhancing memory integration.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.3
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• pp.2131-2134
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• 2015

In this study, It has been demonstrated a new and realizable possibility of the ferroelectric random access memory devices by all solution processing method with paper substrates. Organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) thin films were formed on paper substrate with Al electrode for the bottom gate structure using spin-coating technique. Then, they were subjected to annealing process for crystallization. The fabricated PVDF-TrFE thin films were observed by scanning electron microscopy (SEM) and atomic force microscopy (AFM). It was found from polarization versus electric field (P-E) measurement that a PVDF-TrFE thin film on paper substrate showed very good ferroelectric property. This result agree well with that of a PVDF-TrFE thin film fabricated on the rigid Si substrate. It anticipated that these results will lead to the emergence of printable electron devices on paper. Furthermore, it could be fabricated by a solution processing method for ferroelectric random access memory device, which is reliable and very inexpensive, has a high density, and can be also fabricated easily.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.140-141
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• 2007

To fabricate the metal-ferroelectric-insulator-semiconductor (MFIS) structure for the ferroelectric random access memory (FRAM) application, we prepared the ferroelectric $Sr_{0.9}Bi_{2.1}Ta_2O_9$ (SBT) and the insulator LaZrOx (LZO) thin films on the silicon substrate using a sol-gel method. In this study, we will investigate the feasibility of the SBT/LZO/Si structure as one of the promising gate configuration for the 1-transistor (1-T) type FRAM, by measurements of the electrical properties and the physical properties.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.3
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• pp.49-53
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• 2001

Vortical etching experiments of ($SrBi_2Ta_2O_9$)/Si thin films have been performed by using the inductively coupled plasma reactive ion etching (ICP-ME) apparatus. The purposes of these experiments are to get the effective area of vertical surface. Because this technology is very important to get good qualities of ferroelectric gate structure, capacitor and the minimum parasitic effects related to the excellent performances of the FRAM (Ferroelectric Random Access Memory) device. The reacting gases were Ar and $Cl_2$gases, and various $Ar/C1_2$flow ratios were used. The etching experiments were carried out at various RF powers such as 700, 700, 500W and at various DC powers such as 200, 150, 100, 50W, respectively. The maximum etch rate of $SrBi_2Ta_2O_9$/Si thin films was 1050 A/min at the $Ar/C1_2$ gas ratio of 20/16, RF power of 700 W and DC power of 200 W. From the SEM (scanning electron microscopy) image of the SBT thin films, the wall angle was as good as about $82^{\circ}$.